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SD Memory Card Specifications

Part 1
PHYSICAL LAYER SPECIFICATION
Version 1.01

April 15 2001

SD Group
Matsushita Electric Industrial Co., Ltd. (MEI)
SanDisk Corporation
Toshiba Corporation

CONF IDENT IAL

SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01 SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
Copyright (C)2000 (C)2001 by SD Group (MEI, SanDisk, Toshiba)
Conditions for publication:
-Publisher and Copyright Holder:
SD Group (MEI, SanDisk, Toshiba)

-Confidentiality:
This document shall be treated as confidential under the Non Disclosure Agreement which has been signed by the obtainer.
Reproduction in whole or in part is prohibited without prior written permission of SD Group.
-Exemption:
None will be liable for any damage from use of this document.
Revision History
Date Version
March 22th, 2000 1.0
April 15th, 2001 1.01

Changes compared to previous issue

Base version

-The Supplementary Note (June 2000) that includes clarifications to
the spec was incorporated into the spec.
-Reliability/Durability - the open issues were defined (Torque/
Bending/WP Switch cycles)
-ESD: higher voltages for Non-contact/Air discharge were defined.
- Card’s Thickness tolerance were re-defined for the center area of
the card and more clarifications were added to the WP switch diagram
-Thin SD Card: Mechanical Drawing was added.
-More clarifications were added for SD Read Only Cards.
-Maximum time out for Write/Erase was changed to 250ms.
-Underrun/Overrun status bits were removed (non-relevant in SD
Card) from Table 22.
-Typo fixes and some clarification notes
-Update Fig 31 - Stop Tran during CRC response at Mult Blk WR.
-Add SD ROM Card type in SD_STATUS.
-Fix error in SEND_CID/CSD Ncr timing.
-A clarification about the operating frequency range were added (025Mz
mandatory for SD Card).
-Max Current during initialization period was re-defined.
-Initialization sequence in SPI mode for SD was updated.
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Date: April 2001

2 System features -8

3 SD Memory Card System Concept -9

3.1 Bus Topology - 9
3.1.1 SD bus - 10
3.1.2 SPI bus - 11
3.2 Bus Protocol - 12
3.2.1 SD bus - 12
3.2.2 SPI Bus - 15
3.3 SD Memory Card - Pins and Registers - 17
3.4 Compatibility to MultiMediaCard - 19
4 SD Memory Card Functional Description -22

4.1 General - 22
4.2 Card Identification Mode - 23
4.2.1 Card Reset - 23
4.2.2 Operating Voltage Range Validation - 23
4.2.3 Card Identification Process - 25
4.3 Data Transfer Mode - 25
4.3.1 Wide Bus Selection/Deselection - 27
4.3.2 Data Read - 28
4.3.3 Data Write - 28
4.3.4 Erase - 29
4.3.5 Write Protect Management - 30
4.3.6 Card Lock/Unlock Operation (Optional) - 31
4.3.7 Copyright Protection - 33
4.3.8 Application specific commands - 34
4.4 Clock Control - 35
4.5 Cyclic redundancy codes (CRC) - 36
4.6 Error Conditions - 37
4.6.1 CRC and Illegal Command - 37
4.6.2 Read, Write and Erase Time-out Conditions - 37
4.7 Commands - 38
4.7.1 Command Types - 38
4.7.2 Command Format - 39
4.7.3 Command Classes (Redefined for SD Memory Card) - 39
4.7.4 Detailed Command Description - 40
4.8 Card State Transition Table - 45
4.9 Responses - 47
4.10 SD Memory Card Status - 49
4.10.1 Card Status - 49
4.10.2 SD Status - 52
4.11 Memory Array Partitioning - 53
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SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01 SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
4.12 Timings - 55
4.12.1 Command and Response - 55
4.12.2 Data Read - 56
4.12.3 Data Write - 57
4.12.4 Timing Values -60
5 Card Registers - 61

5.1 OCR Register - 61
5.2 CID Register - 62
5.3 CSD Register - 63
5.4 RCA Register - 72
5.5 DSR Register (Optional) - 72
5.6 SCR Register - 72
6 SD Memory Card Hardware Interface - 74

6.1 Hot insertion and removal - 74
6.2 Card Detection (Insertion/Removal) - 75
6.3 Power protection (Insertion/Removal) - 75
6.4 Power up - 76
6.5 Programmable card output driver (Optional) - 78
6.6 Bus operating conditions - 80
6.7 Bus signal levels - 81
6.8 Bus timing - 82
6.9 Low Voltage (1.8v) SD Memory Cards (Preliminary) - 83
7 SPI Mode - 85

7.1 Introduction - 85
7.2 SPI Bus Protocol - 85
7.2.1 Mode Selection - 85
7.2.2 Bus Transfer Protection - 86
7.2.3 Data Read - 86
7.2.4 Data Write - 87
7.2.5 Erase & Write Protect Management - 89
7.2.6 Read CID/CSD Registers - 89
7.2.7 Reset Sequence - 89
7.2.8 Error Conditions - 90
7.2.9 Memory Array Partitioning - 90
7.2.10 Card Lock/unlock - 90
7.2.11 Application Specific commands - 90
7.2.12 Copyright Protection commands - 90
7.3 SPI Mode Transaction Packets - 90
7.3.1 Command Tokens - 90
7.3.2 Responses - 95
7.3.3 Data Tokens - 98
7.3.4 Data Error Token - 99
7.3.5 Clearing Status Bits - 99
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SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01 SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
7.4 Card Registers - 101
7.5 SPI Bus Timing Diagrams - 101
7.5.1 Command / Response - 102
7.5.2 Data read - 103
7.5.3 Data write - 103
7.5.4 Timing Values - 104
7.6 SPI Electrical Interface - 104
7.7 SPI Bus Operating Conditions - 105
7.8 Bus Timing - 105
8 SD Memory Card mechanical specification - 106

8.1 Card package - 106
8.1.1 External signal contacts (ESC) - 106
8.1.2 Design and format - 107
8.1.3 Reliability and durability - 107
8.1.4 Electrical Static Discharge (ESD) Requirements -108
8.1.5 Quality assurance - 108
8.2 Mechanical form factor - 109
8.3 System: card and connector - 112
8.3.1 Card hot insertion - 112
8.3.2 Inverse insertion - 112
8.3.3 Card Orientation - 113
8.4 Thin (1.4mm) SD Memory Card (Preliminary) - 113
9 Appendix - 116

9.1 Power Supply Decoupling - 116
9.2 Connector - 116
9.2.1 General - 116
9.2.2 Card Insertion and Removal - 117
9.2.3 Characteristics - 118
10 Abbreviations and terms - 121

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SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01 SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
General description

General description

SD Memory Card (Secure Digital Memory Card) is a memory card that is specifically designed to
meet the security, capacity, performance and environment requirements inherent in newly emerging
audio and video consumer electronic devices. The SD Memory Card will include a copyright protection
mechanism that complies with the security of the SDMI standard and will be faster and capable
for higher Memory capacity. The SD Memory Card security system uses mutual authentication and
a "new cipher algorithm" to protect from illegal usage of the card content. A none secured access to
the user‘s own content is also available. The physical form factor, pin assignment and data transfer
protocol are forward compatible with the MultiMediaCard with some additions.

The SD Memory Card communication is based on an advanced 9-pin interface (Clock, Command,
4xData and 3xPower lines) designed to operate in at maximum operating frequency of 25MHz of
and low voltage range. The communication protocol is defined as a part of this specification. The SD
Memory Card host interface supports regular MultiMediaCard operation as well. In other words,
MultiMediaCard forward compatibility was kept. Actually the main difference between SD Memory
Card and MultiMediaCard is the initialization process.

The SD Memory Card Specifications were divided to several documents. The SD Memory Card
documentation structure is given in Figure 1.

Audio Specification other Application Documents
File System Specification
SD Memory Card Physical Layer Spec. (This Document)
SD
Memory
Security
Card
Spec.
Figure 1: SD Memory Card Documentation Structure

‧ SD Memory Card Audio Specification:
This specification along with other application specifications describe the specification of certain
application (in this case - Audio Application) and the requirements to implement it.

‧ SD Memory Card File System Specification:
Describes the specification of the file format structure of the data saved in the SD Memory Card (in
protected and un-protected areas).

‧ SD Memory Card Security Specification:
Describes the copyright protection mechanism and the application specific commands that support
it.

‧ SD Memory Card Physical Layer Specification (this document):
Describes the physical interface and the command protocol used by the SD Memory Card.

The purpose of the SD Memory Card Physical Layer specification is the definition of the SD Memory
Card, its environment and handling.
The document is split up into several portions. Chapter 3 gives a general overview of the system

Date: April 2001

CONFIDENTIAL

SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01 SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
General description

concepts. The common SD Memory Card characteristics are described in Chapter 4. As this
description defines an overall set of card properties, we recommend to use the product documentation
in parallel. The card registers are described in Chapter 5.

Chapter 6 defines the electrical parameters of the SD Memory Card’s hardware interface.

Chapter 8 describes the physical and mechanical properties of the SD Memory Cards and the minimal
recommendations to the card slots or cartridges.
As used in this document, “shall” or “will” denotes a mandatory provision of the standard. “Should”

denotes a provision that is recommended but not mandatory. “May” denotes a feature whose presence
does not preclude compliance, that may or may not be present at the option of the implementor.

Date: April 2001

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SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01 SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
System features

System features

‧
Targeted for portable and stationary applications
‧
Voltage range:
SD Memory Card -
Basic communication (CMD0, CMD15, CMD55, ACMD41): 2.0 - 3.6V
Other commands and memory access: 2.7 - 3.6V

SDLV Memory Card (low voltage) - Operating voltage range: 1.6 - 3.6V

‧
Designed for read-only and read/write cards.
‧
Variable clock rate 0 - 25 MHZ
‧
Up to 10MByte/sec Read/W rite rate (using 4 parallel data lines).
‧
Maximum data rate with up to 10 cards
‧
Correction of memory field errors
‧
Card rem oval during read operation will never harm the content
‧
Forward compatibility to MultiMediaCard
‧
Copyrights Protection Mechanism - Complies with highest security of SDM I standard.
‧
Password Protection of cards (option)
‧
Write Protect feature using mechanical switch
‧
Built-in write protection features (permanent and temporary)
‧
Card Detection (Insertion/Removal)
‧
Application specific commands
‧
Comfortable erase mechanism
‧
Protocol attributes of the comm unication channel:
SD Memory Card Communication Channel

Six-wire communication channel (clock,
command, 4 data lines)

Error-protected data transfer
Single or Multiple block oriented data
transfer

‧ SD Memory Card thickness is defined as either 2.1mm (normal) and 1.4mm (Thin
SD Memory Card) .
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Date: April 2001

SD Memory Card System Concept

The SD Memory Card provides application designers with a low cost mass storage device, implemented
as a removable card, that supports high security level for copyright protection and a compact,
easy-to-implement interface.

SD Memory Cards can be grouped into several card classes which differ in the functions they provide
(given by the subset of SD Memory Card system commands):

‧
Read/Write (RW) cards (Flash, One Time Programmable - OTP, Multiple Time Programmable -
MTP). These cards are typically sold as blank (empty) media and are used for mass data storage,
end user recording of video, audio or digital images.
‧
Read Only Memory (ROM) cards. These cards are manufactured with a fixed data content. They
are typically used as a distribution media for software, audio, video etc.
In terms of operating supply voltage, two types of SD Memory Cards are defined:

‧
SD Memory Cards which supports initialization/identification process with a range of 2.0-3.6v
and operating voltage within this range as defined in the CSD register.
‧
SDLV Memory Cards - Low Voltage SD Memory Cards, that can be operate in voltage range of
1.6-3.6V. The SDLV Memory Cards will be labeled differently then SD Memory Cards.
SD Memory Card system includes the SD Memory Card (or several cards) the bus and their Host /
Application. The Host and Application specification is beyond the scope of this document. The following
sections provides an overview of the card, bus topology and communication protocols of the
SD Memory Card system. The copyright protection (security) system description is given in “SD
Memory Card Security Specification” document.

The SD Memory Card system defines two alternative communication protocols: SD and SPI. Applications
can choose either one of modes. Mode selection is transparent to the host. The card automatically
detects the mode of the reset command and will expect all further communication to be in
the same communication mode. Therefore, applications which uses only one communication mode
do not have to be aware of the other.

3.1 Bus Topology
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3.1.1 SD bus
HOST
CLK
Vdd

Vss
D0-3(A),
CMD(A)

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Figure 2: SD Memory Card system bus Topology
The SD bus includes the following signals:
Host to card clock signal
Bidirectional Command/Response signal
4 Bidirectional data signals.
Power and ground signals.
The SD Memory Card bus has a single master (application), multiple slaves (cards), synchronous
star topology (refer to Figure 2). Clock, power and ground signals are common to all cards. Command
(CMD) and data (DAT0 - DAT3) signals are dedicated to each card providing continues point
to point connection to all the cards.
During initialization process commands are sent to each card individually, allowing the application to
detect the cards and assign logical addresses to the physical slots. Data is always sent (received) to
(from) each card individually. However, in order to simply the handling of the card stack, after the
initialization process, all commands may be sent concurrently to all cards. Addressing information is
provided in the command packet.
SD bus allows dynamic configuration of the number of data lines. After power up, by default, the SD
Memory Card will use only DAT0 for data transfer. After initialization the host can change the bus
width (number of active data lines). This feature allows easy trade off between HW cost and system
SD Memory
Card (A)
CLK
Vdd
Vss
D0-D3, CMD
SD Memory
Card (B)
CLK
Vdd
Vss
D0-D3, CMD
MultiMediaCard
(C)
CLK
Vdd
Vss
D0, CS, CMD
D0-3(B),
CMD(B)
D0-3(C)
CMD(C)
D1&D2 Not
Connected
CLK:

CMD:

DAT0 - DAT3:

VDD, VSS1, VSS2:

performance. Note that while DAT1-DAT3 are not in use, the related Host’s DAT lines should
be in tri-state (input mode).

Date: April 2001

CONFIDENTIAL

SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card System Concept

3.1.2 SPI bus
The SPI compatible communication mode of the SD Memory Card is designed to communicate with
a SPI channel, commonly found in various microcontrollers in the market. The interface is selected
during the first reset command after power up and cannot be changed as long as the part is powered
on.

The SPI standard defines the physical link only, and not the complete data transfer protocol. The SD
Memory Card SPI implementation uses the same command set of the SD mode. From the application
point of view, the advantage of the SPI mode is the capability of using an off-the-shelf host,
hence reducing the design-in effort to minimum. The disadvantage is the loss of performance, relatively
to the SD mode which enables the wide bus option.

The SD Memory Card SPI interface is compatible with SPI hosts available on the market. As any
other SPI device the SD Memory Card SPI channel consists of the following four signals:

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Host to card Chip Select signal.
Host to card clock signal
Host to card data signal.
DataOut: Card to host data signal.
Another SPI common characteristic are byte transfers, which is implemented in the card as well. All
data tokens are multiples of bytes (8 bit) and always byte aligned to the CS signal.
Figure 3: SD Memory Card system (SPI mode) bus topology
Vdd
Vss
CLK,DataIN,DataOut
Vdd
Vdd
Vss
CLK,DataIN,DataOut
Vdd
Vss
CLK,
DataIN,
DataOut
HOST
CLK,DataIN,DataOut
CSCS(B)
CSCS(A)
CSCS(C)
CS:

CLK:

DataIn:

SD Memory
CARD (A)
(SPI mode)
SD Memory
CARD (B)
(SPI mode)
Vss
MultiMediaCard
CARD (C)
(SPI mode)
The card identification and addressing methods are replaced by a hardware Chip Select (CS) signal.
There are no broadcast commands. For every command, a card (slave) is selected by asserting

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SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card System Concept
(active low) the CS signal (see Figure 3).
The CS signal must be continuously active for the duration of the SPI transaction (command,
response and data). The only exception occurs during card programming, when the host can de-
assert the CS signal without affecting the programming process.
The SPI interface uses the 7 out of the SD 9 signals (DAT1 and DAT 2 are not used, DAT3 is the CS
signal) of the SD bus.
3.2 Bus Protocol
3.2.1 SD bus
Communication over the SD bus is based on command and data bit streams which are initiated by a
start bit and terminated by a stop bit.
‧ Command: a command is a token which starts an operation. A command is sent from the host
either to a single card (addressed command) or to all connected cards (broadcast command). A
command is transferred serially on the CMD line.
‧ Response: a response is a token which is sent from an addressed card, or (synchronously) from
all connected cards, to the host as an answer to a previously received command. A response is
transferred serially on the CMD line.
‧ Data: data can be transferred from the card to the host or vice versa. Data is transferred via the
data lines.
Figure 4: “no response” and “no data” operations
Card addressing is implemented using a session address, assigned to the card during the initialization
phase. The structure of commands, responses and data blocks is described in Chapter 4. The
basic transaction on the SD bus is the command/response transaction (refer to Figure 4). This type
of bus transactions transfer their information directly within the command or response structure. In
addition, some operations have a data token.
Data transfers to/from the SD Memory Card are done in blocks. Data blocks always succeeded by
CRC bits. Single and multiple block operations are defined. Note that the Multiple Block operation
mode is better for faster write operation. A multiple block transmission is terminated when a stop
command follows on the CMD line. Data transfer can be configured by the host to use single or multiple
data lines.
command command response
operation (no response) operation (no data)
CMD
DAT
from
host
to card(s)
from
host
to card
from
card
to host
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card System Concept
(active low) the CS signal (see Figure 3).
The CS signal must be continuously active for the duration of the SPI transaction (command,
response and data). The only exception occurs during card programming, when the host can de-
assert the CS signal without affecting the programming process.
The SPI interface uses the 7 out of the SD 9 signals (DAT1 and DAT 2 are not used, DAT3 is the CS
signal) of the SD bus.
3.2 Bus Protocol
3.2.1 SD bus
Communication over the SD bus is based on command and data bit streams which are initiated by a
start bit and terminated by a stop bit.
‧ Command: a command is a token which starts an operation. A command is sent from the host
either to a single card (addressed command) or to all connected cards (broadcast command). A
command is transferred serially on the CMD line.
‧ Response: a response is a token which is sent from an addressed card, or (synchronously) from
all connected cards, to the host as an answer to a previously received command. A response is
transferred serially on the CMD line.
‧ Data: data can be transferred from the card to the host or vice versa. Data is transferred via the
data lines.
Figure 4: “no response” and “no data” operations
Card addressing is implemented using a session address, assigned to the card during the initialization
phase. The structure of commands, responses and data blocks is described in Chapter 4. The
basic transaction on the SD bus is the command/response transaction (refer to Figure 4). This type
of bus transactions transfer their information directly within the command or response structure. In
addition, some operations have a data token.
Data transfers to/from the SD Memory Card are done in blocks. Data blocks always succeeded by
CRC bits. Single and multiple block operations are defined. Note that the Multiple Block operation
mode is better for faster write operation. A multiple block transmission is terminated when a stop
command follows on the CMD line. Data transfer can be configured by the host to use single or multiple
data lines.
command command response
operation (no response) operation (no data)
CMD
DAT
from
host
to card(s)
from
host
to card
from
card
to host
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SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card System Concept
Figure 5: (Multiple) Block read operation
The block write operation uses a simple busy signaling of the write operation duration on the DAT0
data line (see Figure 6) regardless of the number of data lines used for transferring the data.
Figure 6: (Multiple) Block write operation
Command tokens have the following coding scheme:
Figure 7: Command token format
Each command token is preceded by a start bit (‘0’) and succeeded by an end bit (‘1’). The total
length is 48 bits. Each token is protected by CRC bits so that transmission errors can be detected
and the operation may be repeated.
command response command response
block read operation data stop operation
CMD
DAT
from
host
to card
stop command
stops data transfer
data from card
to host
from
card
to host
data block crc
multiple block read operation
command response command response
block write operation data stop operation
CMD
DAT
from
host
to card
stop command
stops data transfer
data from
host
to card
from
card
to host
data block crc
multiple block write operation
busy busy
crc ok
response
and busy
from
card
data block crc data block crc
data block crc
0 1 CONTENT 1
total length=48 bits
start bit:
always’0’
transmitter bit:
’1’= host command
end bit:
always ‘1’
Command content: command and address information
or parameter, protected by 7 bit CRC checksum
CRC
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SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card System Concept
Figure 5: (Multiple) Block read operation
The block write operation uses a simple busy signaling of the write operation duration on the DAT0
data line (see Figure 6) regardless of the number of data lines used for transferring the data.
Figure 6: (Multiple) Block write operation
Command tokens have the following coding scheme:
Figure 7: Command token format
Each command token is preceded by a start bit (‘0’) and succeeded by an end bit (‘1’). The total
length is 48 bits. Each token is protected by CRC bits so that transmission errors can be detected
and the operation may be repeated.
command response command response
block read operation data stop operation
CMD
DAT
from
host
to card
stop command
stops data transfer
data from card
to host
from
card
to host
data block crc
multiple block read operation
command response command response
block write operation data stop operation
CMD
DAT
from
host
to card
stop command
stops data transfer
data from
host
to card
from
card
to host
data block crc
multiple block write operation
busy busy
crc ok
response
and busy
from
card
data block crc data block crc
data block crc
0 1 CONTENT 1
total length=48 bits
start bit:
always’0’
transmitter bit:
’1’= host command
end bit:
always ‘1’
Command content: command and address information
or parameter, protected by 7 bit CRC checksum
CRC
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SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card System Concept
Response tokens have four coding schemes depending on their content. The token length is either
48 or 136 bits. The detailed commands and response definition is given in Chapter 4.7. The CRC
protection algorithm for block data is a 16 bit CCITT polynomial. All used CRC types are described
in Chapter 4.5.
Figure 8: Response token format
In the CMD line the MSB bit is transmitted first the LSB bit is the last.
when the wide bus option is used, the data is transferred 4 bits at a time (refer to Figure 9). Start
and end bits, as well as the CRC bits, are transmitted for every one of the DAT lines. CRC bits are
calculated and checked for every DAT line individually. The CRC status response and Busy indication
will be sent by the card to the host on DAT0 only (DAT1-DAT3 during that period are don’t care).
Figure 9: Data packet format
0 0 CONTENT 1
total length=48 bits
start bit:
always’0’
transmitter bit:
’0’=card response
end bit:
always ‘1’
Response content: mirrored command and status information
(R1 response), OCR register (R3 response) or
RCA (R6), protected by a 7bit CRC checksum
R1, R3,R6
0 0 CONTENT=CID or CSD
total length=136 bits
R2
1
end bit:
always ‘1’
CRC
0 1
block length
start bit:
always’0’
end bit:
always ‘1’
CRCStandard bus (only DAT0 used):
MSB (4095) LSB (0)
0 1
(block length) / 4
start bit:
always’0’
end bit:
always ‘1’
CRCWide bus (all four data lines used):
MSN LSN
0 1CRC
0 1CRC
0 1CRC
DAT3
DAT2
DAT1
DAT0
4095
4094
4093
4092
3
2
1
0
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card System Concept
Response tokens have four coding schemes depending on their content. The token length is either
48 or 136 bits. The detailed commands and response definition is given in Chapter 4.7. The CRC
protection algorithm for block data is a 16 bit CCITT polynomial. All used CRC types are described
in Chapter 4.5.
Figure 8: Response token format
In the CMD line the MSB bit is transmitted first the LSB bit is the last.
when the wide bus option is used, the data is transferred 4 bits at a time (refer to Figure 9). Start
and end bits, as well as the CRC bits, are transmitted for every one of the DAT lines. CRC bits are
calculated and checked for every DAT line individually. The CRC status response and Busy indication
will be sent by the card to the host on DAT0 only (DAT1-DAT3 during that period are don’t care).
Figure 9: Data packet format
0 0 CONTENT 1
total length=48 bits
start bit:
always’0’
transmitter bit:
’0’=card response
end bit:
always ‘1’
Response content: mirrored command and status information
(R1 response), OCR register (R3 response) or
RCA (R6), protected by a 7bit CRC checksum
R1, R3,R6
0 0 CONTENT=CID or CSD
total length=136 bits
R2
1
end bit:
always ‘1’
CRC
0 1
block length
start bit:
always’0’
end bit:
always ‘1’
CRCStandard bus (only DAT0 used):
MSB (4095) LSB (0)
0 1
(block length) / 4
start bit:
always’0’
end bit:
always ‘1’
CRCWide bus (all four data lines used):
MSN LSN
0 1CRC
0 1CRC
0 1CRC
DAT3
DAT2
DAT1
DAT0
4095
4094
4093
4092
3
2
1
0
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Date: April 2001

CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card System Concept
3.2.2 SPI Bus
While the SD channel is based on command and data bit streams which are initiated by a start bit
and terminated by a stop bit, the SPI channel is byte oriented. Every command or data block is built
of 8-bit bytes and is byte aligned to the CS signal (i.e. the length is a multiple of 8 clock cycles).
Similar to the SD protocol, the SPI messages consist of command, response and data-block tokens
All communication between host and cards is controlled by the host (master). The host starts every
bus transaction by asserting the CS signal low.
The response behavior in the SPI mode differs from the SD mode in the following three aspects:
‧ The selected card always responds to the command.
‧ Two new (8 & 16 bit) response structure is used
‧ When the card encounters a data retrieval problem, it will respond with an error response (which
replaces the expected data block) rather than by a time-out as in the SD mode.
In addition to the command response, every data block sent to the card during write operations will
be responded with a special data response token.
‧ Data Read
Single and multiple block read commands are supported in SPI mode. However, in order to comply
with the SPI industry standard, only two (unidirectional) signal are used (refer to Chapter 10). Upon
reception of a valid read command the card will respond with a response token followed by a data
token of the length defined in a previous SET_BLOCKLEN (CMD16) command. A multiple block
read operation is terminated, similar to the SD protocol, with the STOP_TRANSMISSION command.
Figure 10: Read operation
A valid data block is suffixed with a 16 bit CRC generated by the standard CCITT polynomial
x16+x12+x5+1.
In case of a data retrieval error, the card will not transmit any data. Instead, a special data error
token will be sent to the host. Figure 11 shows a data read operation which terminated with an error
commandDataIn
DataOut
from
host
to card
data from card
to host
from
card
to host
data blockresponse
command
stop Command
CRC data block CRC response
block read operation
data stop operation
multiple block read operation
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card System Concept
3.2.2 SPI Bus
While the SD channel is based on command and data bit streams which are initiated by a start bit
and terminated by a stop bit, the SPI channel is byte oriented. Every command or data block is built
of 8-bit bytes and is byte aligned to the CS signal (i.e. the length is a multiple of 8 clock cycles).
Similar to the SD protocol, the SPI messages consist of command, response and data-block tokens
All communication between host and cards is controlled by the host (master). The host starts every
bus transaction by asserting the CS signal low.
The response behavior in the SPI mode differs from the SD mode in the following three aspects:
‧ The selected card always responds to the command.
‧ Two new (8 & 16 bit) response structure is used
‧ When the card encounters a data retrieval problem, it will respond with an error response (which
replaces the expected data block) rather than by a time-out as in the SD mode.
In addition to the command response, every data block sent to the card during write operations will
be responded with a special data response token.
‧ Data Read
Single and multiple block read commands are supported in SPI mode. However, in order to comply
with the SPI industry standard, only two (unidirectional) signal are used (refer to Chapter 10). Upon
reception of a valid read command the card will respond with a response token followed by a data
token of the length defined in a previous SET_BLOCKLEN (CMD16) command. A multiple block
read operation is terminated, similar to the SD protocol, with the STOP_TRANSMISSION command.
Figure 10: Read operation
A valid data block is suffixed with a 16 bit CRC generated by the standard CCITT polynomial
x16+x12+x5+1.
In case of a data retrieval error, the card will not transmit any data. Instead, a special data error
token will be sent to the host. Figure 11 shows a data read operation which terminated with an error
commandDataIn
DataOut
from
host
to card
data from card
to host
from
card
to host
data blockresponse
command
stop Command
CRC data block CRC response
block read operation
data stop operation
multiple block read operation
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CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card System Concept
token rather than a data block.
Figure 11: Read operation - data error
‧ Data W rite
Single and multiple block write operations are supported in SPI mode. Upon reception of a valid
write command, the card will respond with a response token and will wait for a data block to be sent
from the host. CRC suffix, block length and start address restrictions are identical to the read operation
(see Figure 12).
Figure 12: W rite operation
After a data block has been received, the card will respond with a data-response token. If the data
block has been received without errors, it will be programmed. As long as the card is busy programming,
a continuous stream of busy tokens will be sent to the host (effectively holding the DataOut
line low).
commandDataIn
DataOut
from
host
to card
data error token
from card to host
from
card
to host
data error response
command
Next
Command
Data Resp
commandDataIn
DataOut
from
host
to card
data from
host
to card
from
card
to host
data block
busy
Data
response and
busy from
card
response
>
data start
token
data from
host
to card
data block>
Data Resp busy
<
data stop
token
block write operation
data stop operation
multiple block write operation
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card System Concept
token rather than a data block.
Figure 11: Read operation - data error
‧ Data W rite
Single and multiple block write operations are supported in SPI mode. Upon reception of a valid
write command, the card will respond with a response token and will wait for a data block to be sent
from the host. CRC suffix, block length and start address restrictions are identical to the read operation
(see Figure 12).
Figure 12: W rite operation
After a data block has been received, the card will respond with a data-response token. If the data
block has been received without errors, it will be programmed. As long as the card is busy programming,
a continuous stream of busy tokens will be sent to the host (effectively holding the DataOut
line low).
commandDataIn
DataOut
from
host
to card
data error token
from card to host
from
card
to host
data error response
command
Next
Command
Data Resp
commandDataIn
DataOut
from
host
to card
data from
host
to card
from
card
to host
data block
busy
Data
response and
busy from
card
response
>
data start
token
data from
host
to card
data block>
Data Resp busy
<
data stop
token
block write operation
data stop operation
multiple block write operation
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Date: April 2001

3.3 SD Memory Card - Pins and Registers
The SD Memory Card has the form factor 24mm x 32mm x 2.1mm.

1 2 3 45 678

SD Memory
Card

Figure 13: SD Memory Card shape and interface (top view)

Figure 13 describes the general idea of the shape and interface contacts of SD Memory Card. The
detailed physical dimensions and mechanical description is given in chapter 9.
The following table defines the card contacts:

Table 1: SD memory Card Pad Assignment

1)
S: power supply; I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers;

2)
The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after
SET_BUS_WIDTH command. The Host shall keep its own DAT1-DAT3 lines in input mode, as well,
while they are not used. It is defined so, in order to keep compatibility to MultiMediaCards.

3)
After power up this line is input with 50KOhm pull-up (can be used for card detection or SPI mode selection).
The pull-up should be disconnected by the user, during regular data transfer, with
SET_CLR_CARD_DETECT (ACMD42) command

Each card has a set of information registers (see also Chapter 5 in the SD Memory Card Physical

Pin #
SD Mode SPI Mode
Name Type1 Description Name Type Description
1 CD/DAT32 I/O/PP3 Card Detect /
Data Line [Bit 3]TaisolCS I Chip Select (neg true)
2 CMD PP Command/Response DI I Data In
3 VSS1 S Supply voltage ground VSS S Supply voltage ground
4 VDD S Supply voltage VDD S Supply voltage
5 CLK I Clock SCLK I Clock
6 VSS2 S Supply voltage ground VSS2 S Supply voltage ground
7 DAT0 I/O/PP Data Line [Bit 0] DO O/PP Data Out
8 DAT1 I/O/PP Data Line [Bit 1] RSV
9 DAT2 I/O/PP Data Line [Bit 2] RSV

Date: April 2001

CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card System Concept
Layer Specification):
The host may reset the cards by switching the power supply off and on again. Each card shall have
its own power-on detection circuitry which puts the card into a defined state after the power-on. No
explicit reset signal is necessary. The cards can also be reset by sending the GO_IDLE (CMD0)
command.
Figure 14: SD Memory Card architecture
Name W idth Description
CID 128 Card identification number; card individual number for identification. Mandatory.
RCA1
1) RCA register is not used (available) in SPI mode.
16 Relative card address; local system address of a card, dynamically suggested by the
card and approved by the host during initialization. Mandatory.
DSR 16 Driver Stage Register; to configure the card’s output drivers. Optional.
CSD 128 Card Specific Data; information about the card operation conditions. Mandatory
SCR 64 SD Configuration Register; information about the SD Memory Card’s Special Features
capabilities. Mandatory
OCR 32 Operation condition register. Mandatory.
Table 2: SD Memory Card registers
RCA[15:0]
CID[127:0]
DSR[15:0]
CSD[127:0]
Card
interface
controller
Memory core
Memory core interface
CMD CLK DAT0
Power on detection
reset
Interface driver
VDD
OCR[31:0]
reset
SCR[63:0]
DAT1
DAT2
CD/DAT3
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card System Concept
Layer Specification):
The host may reset the cards by switching the power supply off and on again. Each card shall have
its own power-on detection circuitry which puts the card into a defined state after the power-on. No
explicit reset signal is necessary. The cards can also be reset by sending the GO_IDLE (CMD0)
command.
Figure 14: SD Memory Card architecture
Name W idth Description
CID 128 Card identification number; card individual number for identification. Mandatory.
RCA1
1) RCA register is not used (available) in SPI mode.
16 Relative card address; local system address of a card, dynamically suggested by the
card and approved by the host during initialization. Mandatory.
DSR 16 Driver Stage Register; to configure the card’s output drivers. Optional.
CSD 128 Card Specific Data; information about the card operation conditions. Mandatory
SCR 64 SD Configuration Register; information about the SD Memory Card’s Special Features
capabilities. Mandatory
OCR 32 Operation condition register. Mandatory.
Table 2: SD Memory Card registers
RCA[15:0]
CID[127:0]
DSR[15:0]
CSD[127:0]
Card
interface
controller
Memory core
Memory core interface
CMD CLK DAT0
Power on detection
reset
Interface driver
VDD
OCR[31:0]
reset
SCR[63:0]
DAT1
DAT2
CD/DAT3
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Date: April 2001

3.4 Compatibility to MultiMediaCard
The SD Memory Card protocol is designed to be a super-set of the MultiMediaCard protocol1. The
main additions are the wide bus option and the content protection support (refer to Table 3 for
details). It is very easy to design host systems, capable of supporting both types of cards. The intent
is to enable application designers to make use of the exiting install base of MultiMediaCard, unless
the application cannot do without either the fast data transfer rate (wide bus), or content security.

SD Memory Card

MultiMediaCard

Comments

Bus width

1bit or 4 bits

1 bit only

System bus organization

Star Topology

Bus Topology

(multiple cards connection)

Initialization commands

CMD0 CMD0

In MultiMediaCard CMD1 and
ACMD41

CMD1

CMD2 are sent concurrently from
CMD2

CMD2

all cards using the OD drivers. In
CMD3

CMD3

SD memory card each card is
reset and identified independently
and the RCA (CMD3) is
assigned by the card.

two new command for improved
write performance (ACMD23,
ACMD22) are supported in SD.

When MultiMediaCard is inserted
into an SD Memory Card slot, it
always perceived as non-writeprotected
card (window closed)

In SD Memory Card pin #1 may
be used for card detection.

Different from MMC In SD the Manufacturing date
field is bigger. Product ID field is
smaller.

Supported

Not supported
not supported

supported

SD Memory Card supports only
(optional)

single and multiple block read/
write operations.

SEND_NUM_WR_BLOCK
SET_WR_BLK_COUNT

25MHz

20MHz
supported (optional in

not supported
Read Only type of cards)

supported

not supported

Has a card internal pull-up

Defined as "not
resistor

connected"

Different from MMC
(mainly Sector Size/
Groups is different)

Operation Commands

Maximum Clock rate

Write protect switch

Feature of Pin #1

CSD Structure

CID Structure

SPI R/W Multiple Block

Stream R/W mode

1. As defined in the MultiMediaCard system specification V2.11. Published by the MMCA technical commitee.
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Date: April 2001

SD Memory Card MultiMediaCard CommentsI/O Mode not supported supported I/O (Interrupt) mode is not sup(
optional) ported in SD Memory Card.

Table 3: Differences between SD Memory Card and MultiMediaCard Feature set

The only difference (as opposed to addition) between the SD Memory Card and the MultiMediaCard
is the bus topology and initialization protocol. While the MultiMediaCard stack is connected on the
same bus and being identified using synchronous transmission of Open-drain outputs, each SD
Memory Card has an independent point-to-point connection to the host, and the cards are identified
serially, one at a time (refer to Table 4 for a command set comparison between SD Memory Card
and MultiMediaCard. Detailed description of the SD Memory card protocol commands can be found
in Chapter 4).

The initializing procedure in the SD protocol is defined to successfully identify either a MultiMediaCard
or a SD Memory Card, which ever is currently connected on the bus. After card detection, the
host executes the initializing procedure and ends up with an identified card of a known type.

Once the card is initialized the application can determine the card capabilities by querying the vari

ous configuration registers, and decide whether or not to use it.
The physical dimension of the SD Memory Card is thicker than MultiMediaCard (2.1mm vs. 1.4mm;
refer to Chapter 9) but it is defined in such a way that a MultiMediaCard can be inserted into SD
Memory Card socket. Note that because of the small differences between the mechanical definition
of the pads layout of MultiMediaCard it is required that the SD Host will set its own DAT1-DAT3 lines
to be in Input Mode (Tri-State) while they are not in use.

Three different card detect mechanisms are defined for the SD Memory Card (e.g. mechanical
insertion which can be sensed using the WP switch, Electrical insertion which can be sensed using
the pull-up resistor on DAT3 and periodical attempts to initialize the card). Since some of these
methods may be not relevant (or behave differently) for the MultiMediaCard, it is recommended not
to depend on the preemptive card detects methods only. The host should implement a polling
mechanism or allow the operator to request card identification.

SD Memory

CMD0
(Mandatory)
CMD0 Same command.Class 0 CMD0
ReservedCMD1 CMD1 In SD Memory Card ACMD41 is used instead of CMD1
(Mandatory)
CMD2 CMD2 CMD2 Similar command except buffer type used to transmit
to response of the card. (SD Memory Card: push-pull,
MultiMediaCard: open-drain)
(Mandatory)
CMD3 CMD3 CMD3 In both protocols this command is used to assign a
logical address to the card. While In MultiMediaCard
the host assigned the address, in SD memory Card it
is the responsibility of the card.
CMD4-10CMD CMD4-10 Same commands.

MultiMedia

Comment

Card

Class

CMD

Card

(Mandatory)

4-10

Table 4: Commands comparison table.

Date: April 2001

Class

Class 1

Class 0

Class 2

Class 3

CMD

CMD11

CMD12
-15

CMD16
-19

CMD20

CMD21
-23

SD Memory
Card

Reserved

CMD12-15
(Mandatory)

CMD16-19
(Mandatory)

Reserved

MultiMedia
Card

CMD11

CMD12-15

CMD16-19

CMD20

Reserved

Comment

SD Memory Card doesn’t support stream access.

Same commands.

SD Memory Card dose not support stream access.

All reserved.

CMD24-27
(Mandatory for
Writable card)
CMD24-27 Same commands.
ElectronicsCMD28-31
(Optional)
CMD28-31 Same commands.
CMD32-33
(Mandatory for
Writable card)
CMD32-33 Same commands.TaisolReserved CMD34-37 SD Memory Card dose not support TAG and Erase
Group commands
CMD38
(Mandatory for
Writable card)
CMD38 Same Command.
Reserved CMD39-41 SD Memory Card dose not support I/O mode.
CMD42-54
(Optional)
CMD42-54 Same commands.
CMD55-56
(Mandatory)
CMD55-56 Same commands.
CMD60-63
(reserved for
manufac(
reserved
for manuCMD60-
63

facturer)

Table 4: Commands comparison table.

Class 4

CMD24

-27

Class 6

CMD28

-31

CMD32

-33

Class 5

CMD34

-37

CMD38

Class 9

CMD39

-41

Class 7

CMD42

-54

CMD55

-56

CMD60

Class 8

-63

turer)

Date: April 2001

4 SD Memory Card Functional Description

4.1 General
All communication between host and cards is controlled by the host (master). The host sends commands
of two types: broadcast and addressed (point-to-point) commands.

‧ Broadcast commands
Broadcast commands are intended for all cards. Some of these commands require a response.

‧ Addressed (point-to-point) comm ands
The addressed commands are sent to the addressed card and cause a response from this card.
A general overview of the command flow is shown in Figure 15 for the card identification mode and

in Figure for the data transfer mode. The commands are listed in the command tables (Table 9 Table
16). The dependencies between current state, received command and following state are
listed in Table 17. In the following sections, the different card operation modes will be described
first. Thereafter, the restrictions for controlling the clock signal are defined. All SD Memory Card
commands together with the corresponding responses, state transitions, error conditions and timings
are presented in the succeeding sections.

Two operation modes are defined for the SD Memory Card system (host and cards):

dentification mode

The host will be in card identification mode after reset and while it is looking for new cards on

the bus. Cards will be in this mode after reset until the SEND_RCA command (CMD3) is

Inactive State

inactive
Idle State

card identification mode

Ready State
Identification State
Stand-by State
Transfer State
Sending-data State

data transfer mode

Receive-data State
Programming State
Disconnect State

‧ Card i
received (in case of MultiMediaCard - SET_RCA command).

Cards will enter data transfer mode once their RCA is first published. The host will enter data

transfer mode after identifying all the cards on the bus.

The following table shows the dependencies between operation modes and card states. Each state
in the SD Memory Card state diagram (see Figure 15 and Figure ) is associated with one operation

Card state

Operation mode

‧ Data transfer mode
mode:

Table 5: Overview of Card States vs. Operation modes

Date: April 2001

4.2 Card Identification Mode
While in card identification mode the host resets all the cards that are in card identification mode,
validates operation voltage range, identifies cards and asks them to publish Relative Card Address
(RCA). This operation is done to each card separately on its own CMD line. All data communication
in the Card Identification Mode uses the command line (CMD) only.

4.2.1 Card Reset
The command GO_IDLE_STATE (CMD0) is the software reset command and sets each card into
Idle State regardless of the current card state. Cards in Inactive State are not affected by this command.

After power-on by the host, all cards are in Idle State, including the cards that have been in Inactive

After power-on or CMD0, all cards’ CMD lines are in input mode, waiting for start bit of the next command.
The cards are initialized with a default relative card address (RCA=0x0000) and with a
default driver stage register setting (lowest speed, highest driving current capability).

Operating Voltage Range Validation

All cards shall be able to establish communication with the host using any operating voltage in the
maximal allowed voltage range specified in this standard (see Chapter 6.6). However, the supported
minimum and maximum values for VDD are defined in the Operation Conditions Register
(OCR) and may not cover the whole range. Cards that store the CID and CSD data in the payload
memory would be able to communicate these information only under data transfer VDD conditions.
That means if host and card have non compatible VDD ranges, the card will not be able to complete
the identification cycle, nor to send CSD data.

Therefore, a special command SD_SEND_OP_COND (ACMD41) is designed to provide SD Memory
Card hosts with a mechanism to identify and reject cards which do not match the VDD range
desired by the host. This is accomplished by the host sending the required VDD voltage window as
the operand of this command (See Chapter 5.1). Cards which can not perform data transfer in the
specified range must discard themselves from further bus operations and go into Inactive State. The
levels in the OCR register shall be defined accordingly (see Chapter 5.1). Note that ACMD41 is
application specific command, therefore APP_CMD (CMD55) shall always precede ACMD41. The
RCA to be used for CMD55 in idle_state shall be the card’s default RCA = 0x0000.

The MultiMediaCard will not respond to ACMD41 (actually it will not respond to APP_CMD CMD55,
that preceding it). MultiMediaCard shall be initialized as per the MultiMediaCard spec,
using SEND_OP_COND command (CMD1 of MultiMediaCard). The host should ignore an
ILLEGAL_COMMAND status in the MultiMediaCard response to CMD3, as it is a residue of
ACMD41 which is invalid in MultiMediaCard (CMD0, 1, 2 do not clear the status register). Actually,
ACMD41 and CMD1 will be used by the host to distinguish between MultiMediaCard and SD Mem-

State before.

4.2.2

ory Cards in a system.

Date: April 2001

CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
Figure 15: SD Memory Card state diagram (card identification mode)
By omitting the voltage range in the command, the host can query each card and determine the
common voltage range before sending out-of-range cards into the Inactive State. This query should
be used if the host is able to select a common voltage range or if a notification to the application of
non usable cards in the stack is desired. Afterwards, the host must choose a voltage for operation
and reissue ACMD41 with this condition, sending incompatible cards into the Inactive State.
The busy bit in the ACMD41 response can be used by a card to tell the host that it is still working on
its power-up/reset procedure (e.g. downloading the register information from memory field) and is
not ready yet for communication. In this case the host must repeat ACMD41 until the busy bit is
cleared.
During the initialization procedure, the host is not allowed to change the operating voltage range.
Such changes shall be ignored by the card. If there is a real change in the operating conditions, the
host must reset the card stack (sending CMD0 to all cards) and restart the initialization procedure.
However, for accessing also the cards being already in Inactive State, a hard reset must be done by
switching the power supply off and on.
The command GO_INACTIVE_STATE (CMD15) can be used to send an addressed card into the
ACMD41 Inactive
State (ina)
Idle State
(idle)
Identification
State (ident)
CMD0
CMD3
from all states except (ina)
from all states in
CMD15
cards with non compatible voltage range
card is busy or
data-transfer-modeStand-by State
(stby)
Power on
host omitted voltage
range
CMD3
Card responds with
new RCA
Card responds with
new RCA
Ready State
(ready)
CMD2
data-transfer mode
card-identification mode
Start MultiMediaCard
(Non valid command)
Must be a
MultiMediaCard
initialization process
starting at CMD1
No Response
SPI Operation
Mode
CMD0 +
CS Asserted (“0”)
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
Figure 15: SD Memory Card state diagram (card identification mode)
By omitting the voltage range in the command, the host can query each card and determine the
common voltage range before sending out-of-range cards into the Inactive State. This query should
be used if the host is able to select a common voltage range or if a notification to the application of
non usable cards in the stack is desired. Afterwards, the host must choose a voltage for operation
and reissue ACMD41 with this condition, sending incompatible cards into the Inactive State.
The busy bit in the ACMD41 response can be used by a card to tell the host that it is still working on
its power-up/reset procedure (e.g. downloading the register information from memory field) and is
not ready yet for communication. In this case the host must repeat ACMD41 until the busy bit is
cleared.
During the initialization procedure, the host is not allowed to change the operating voltage range.
Such changes shall be ignored by the card. If there is a real change in the operating conditions, the
host must reset the card stack (sending CMD0 to all cards) and restart the initialization procedure.
However, for accessing also the cards being already in Inactive State, a hard reset must be done by
switching the power supply off and on.
The command GO_INACTIVE_STATE (CMD15) can be used to send an addressed card into the
ACMD41 Inactive
State (ina)
Idle State
(idle)
Identification
State (ident)
CMD0
CMD3
from all states except (ina)
from all states in
CMD15
cards with non compatible voltage range
card is busy or
data-transfer-modeStand-by State
(stby)
Power on
host omitted voltage
range
CMD3
Card responds with
new RCA
Card responds with
new RCA
Ready State
(ready)
CMD2
data-transfer mode
card-identification mode
Start MultiMediaCard
(Non valid command)
Must be a
MultiMediaCard
initialization process
starting at CMD1
No Response
SPI Operation
Mode
CMD0 +
CS Asserted (“0”)
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Date: April 2001

Inactive State. This command is used when the host explicitly wants to deactivate a card (e.g. host
is changing VDD into a range which is known to be not supported by this card).

4.2.3 Card Identification Process
The host starts the card identification process with the identification clock rate fOD (see Chapter

6.8). In SD Memory Card the CMD line output drives are push-pull drivers.
After the bus is activated the host will request the cards to send their valid operation conditions
(ACMD41 preceding with APP_CMD - CMD55 with RCA=0x0000). The response to ACMD41 is the
operation condition register of the card. The same command shall be send to all of the new cards in
the system. Incompatible cards are sent into Inactive State. The host then issues the command

ALL_SEND_CID (CMD2), to each card to get its unique card identification (CID) number. Card that
is unidentified (i.e. which is in Ready State) sends its CID number as the response (on the CMD
line). After the CID was sent by the card it goes into Identification State. Thereafter, the host issues
CMD3 (SEND_RELATIVE_ADDR) asks the card to publish a new relative card address (RCA),
which is shorter than CID and which will be used to address the card in the future data transfer
mode (typically with a higher clock rate than fOD). Once the RCA is received the card state changes
to the Stand-by State. At this point, if the host wants that the card will have another RCA number, it
may ask the card to publish a new number by sending another SEND_RELATIVE_ADDR command

The broadcast command SET_DSR (CMD4) configures the driver stages of all identified cards. It
programs their DSR registers corresponding to the application bus layout (length) and the number
of cards on the bus and the data transfer frequency. The clock rate is also switched from fOD to fPP
at that point. SET_DSR command is an option for the card and the host.

CMD7 is used to select one card and put it into the Transfer State. Only one card can be in the
Transfer State at a given time. If a previously selected card is in the Transfer State its connection
with the host is released and it will move back to the Stand-by State. When CMD7 is issued with the

to the card. The last published RCA is the actual RCA number of the card.
The host repeats the identification process, i.e. the cycles with CMD2 and CMD3 for each card in

After all the SD Memory Cards were initialized the host shall initialize the MultiMediaCards that are
in the system (if any), using the CMD2 and CMD3 as given in the MultiMediaCard spec. Note that in
the SD system all the cards are connected separately so each MultiMediaCard shall be initialized

Data Transfer Mode

Until the end of Card Identification Mode the host must remain at fOD frequency because some
cards may have operating frequency restrictions during the card identification mode. In Data Transfer
Mode the host may operate the card in fPP frequency range (see chapter 6.8). The host issues
SEND_CSD (CMD9) to obtain the Card Specific Data (CSD register), e.g. block length, card storage

the system.

individually.

capacity, etc.

reserved relative card address “0x0000”, all cards are put back to Stand-by State (Note that it is the

Date: April 2001

CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
Figure 16: SD Memory Card state diagram (data transfer mode)
responsibility of the Host to reserve the RCA=0 for card de-selection - refer to Table 9, CMD7
description). This may be used before identifying new cards without resetting other already registered
cards. Cards which already have an RCA do not respond to identification commands (CMD41,
CMD2, CMD3, see Chapter 4.2.3) in this state.
Important Note: The card de-selection is done if certain card gets CMD7 with un-matched RCA.
That happens automatically if selection is done to another card and the CMD lines are common. So,
in SD Memory Card system it will be the responsibility of the host either to work with common CMD
line (after initialization is done) - in that case the card de-selection will be done automatically (as in
MultiMediaCard system) or if the CMD lines are separate then the host shall be aware to the necessity
to de-select cards.
All data communication in the Data Transfer Mode is point-to point between the host and the
selected card (using addressed commands). All addressed commands get acknowledged by a
response on the CMD line.
State (tran)
Stand-by State(stby)
Transfer
Sending-data
State (data)
CMD3
CMD4,
CMD7
9,10,3
CMD16,
CMD7
CMD17,18,30,56(r)
ACMD51
data transfer
card identification
CMD13, CMD55
in data-transfer-mode
no state transition
CMD12,
“operation
32..37
State (rcv)
Receive-data
CMD24,25,26,27,42,56(w)
CMD15
from all states in
data-transfer-mode
State (prg)
Programming
CMD28,29,38
“operation
complete”
State (dis)
Disconnect
CMD7
“operation
complete”
CMD0
CMD7
complete”
CMD12 or
.transfer end“
mode
mode
ACMD6,13,42ACMD22,23
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
Figure 16: SD Memory Card state diagram (data transfer mode)
responsibility of the Host to reserve the RCA=0 for card de-selection - refer to Table 9, CMD7
description). This may be used before identifying new cards without resetting other already registered
cards. Cards which already have an RCA do not respond to identification commands (CMD41,
CMD2, CMD3, see Chapter 4.2.3) in this state.
Important Note: The card de-selection is done if certain card gets CMD7 with un-matched RCA.
That happens automatically if selection is done to another card and the CMD lines are common. So,
in SD Memory Card system it will be the responsibility of the host either to work with common CMD
line (after initialization is done) - in that case the card de-selection will be done automatically (as in
MultiMediaCard system) or if the CMD lines are separate then the host shall be aware to the necessity
to de-select cards.
All data communication in the Data Transfer Mode is point-to point between the host and the
selected card (using addressed commands). All addressed commands get acknowledged by a
response on the CMD line.
State (tran)
Stand-by State(stby)
Transfer
Sending-data
State (data)
CMD3
CMD4,
CMD7
9,10,3
CMD16,
CMD7
CMD17,18,30,56(r)
ACMD51
data transfer
card identification
CMD13, CMD55
in data-transfer-mode
no state transition
CMD12,
“operation
32..37
State (rcv)
Receive-data
CMD24,25,26,27,42,56(w)
CMD15
from all states in
data-transfer-mode
State (prg)
Programming
CMD28,29,38
“operation
complete”
State (dis)
Disconnect
CMD7
“operation
complete”
CMD0
CMD7
complete”
CMD12 or
.transfer end“
mode
mode
ACMD6,13,42ACMD22,23
DO NOT COPY (c)2000 (c)2001 by SD Group (MEI,SanDisk,Toshiba)

Date: April 2001

The relationship between the various data transfer modes is summarized below (see Figure ):

‧
All data read commands can be aborted any time by the stop command (CMD12). The data
transfer will terminate and the card will return to the Transfer State. The read commands are:
block read (CMD17), multiple block read (CMD18), send write protect (CMD30), send scr
(ACMD51) and general command in read mode (CMD56).
‧
All data write commands can be aborted any time by the stop command (CMD12). The write
commands must be stopped prior to deselecting the card by CMD7. The write commands are:
block write (CMD24 and CMD25), write CID (CMD26), write CSD (CMD27), lock/unlock command
(CMD42) and general command in write mode (CMD56).
‧
As soon as the data transfer is completed, the card will exit the data write state and move either
‧

to the Programming State (transfer is successful) or Transfer State (transfer failed).
If a block write operation is stopped and the block length and CRC of the last block are valid, the
data will be programmed.

‧
The card may provide buffering for block write. This means that the next block can be sent to the
card while the previous is being programmed.
If all write buffers are full, and as long as the card is in Programming State (see SD Memory Card
‧

‧

‧
‧

‧

‧
Resetting a card (using CMD0 or CMD15) will terminate any pending or active programming
operation. This may destroy the data contents on the card. It is the host’s responsibility to pre-
Wide Bus (4 bit bus width) operation mode may be selected/deselected using ACMD6. The default
bus width after power up or GO_IDLE (CMD0) is 1 bit bus width. ACMD6 command is valid in ‘tran
state‘ only. That means that the bus width may be changed only after a card was selected (CMD7).

state diagram Figure ), the DAT0 line will be kept low (BUSY).
There is no buffering option for write CSD, write CID, write protection and erase. This means that
while the card is busy servicing any one of these commands, no other data transfer commands
will be accepted. DAT0 line will be kept low as long as the card is busy and in the Programming
State. Actually if the CMD and DAT0 lines of the cards are kept separated and the host keep the
busy DAT0 line disconnected from the other DAT0 lines (of the other cards) the host may access
the other cards while the card is in busy.
Parameter set commands are not allowed while card is programming.
Parameter set commands are: set block length (CMD16), erase block start (CMD32) and erase

Read commands are not allowed while card is programming.
Moving another card from Stand-by to Transfer State (using CMD7) will not terminate erase and
programming operations. The card will switch to the Disconnect State and will release the DAT

A card can be reselected while in the Disconnect State, using CMD7. In this case the card will
move to the Programming State and reactivate the busy indication.

block end (CMD33).

line.

vent this.

4.3.1 W ide Bus Selection/Deselection
DO NOT COPY (c)2000 (c)2001 by SD Group (MEI,SanDisk,Toshiba)

Date: April 2001

4.3.2 Data Read
The DAT bus line level is high by the pull-up when no data is transmitted. A transmitted data block
consists of start bits (1 or 4 bits LOW), followed by a continuous data stream. The data stream contains
the payload data (and error correction bits if an off-card ECC is used). The data stream ends
with end bits (1 or 4 bits HIGH) (see Figure 25-Figure 27). The data transmission is synchronous to
the clock signal. The payload for block oriented data transfer is protected by 1 or 4 bits CRC check
sum (see Chapter 3.2).

The Read operation from SD Memory Card may be interrupted by turning the power off. The SD
Memory Card ensures that data is not destroyed during all the conditions except write or erase
operations issued by the host even in the event of sudden shut down or removal.

‧ Block Read
Block read is block oriented data transfer. The basic unit of data transfer is a block whose maximum
size is defined in the CSD (READ_BL_LEN). Smaller blocks whose starting and ending address are
entirely contained within one physical block (as defined by READ_BL_LEN) may also be transmitted.
It is a mandatory requirement that SD Memory Card shall have a capability to transfer blocks of

A CRC is appended to the end of each block ensuring data transfer integrity. CMD17
(READ_SINGLE_BLOCK) initiates a block read and after completing the transfer, the card returns
to the Transfer State. CMD18 (READ_MULTIPLE_BLOCK) starts a transfer of several consecutive
blocks. Blocks will be continuously transferred until a STOP_TRANSMISSION command (CMD12)
is issued. The stop command has an execution delay due to the serial command transmission. The
data transfer stops after the end bit of the stop command.

If the host uses partial blocks whose accumulated length is not block aligned and block misalignment
is not allowed, the card shall detect a block misalignment at the beginning of the first misaligned
block, set the ADDRESS_ERROR error bit in the status register, abort transmission and
wait in the Data State for a stop command.

The data transfer format is similar to the data read format. For block oriented write data transfer, the
CRC check bits are added to each data block. The card performs 1 or 4 bits CRC parity check (see
Chapter 7.2) for each received data block prior to the write operation. By this mechanism, writing of
erroneously transferred data can be prevented.

During block write (CMD24 - 27,42,56(w)) one or more blocks of data are transferred from the host
to the card with 1 or 4 bits CRC appended to the end of each block by the host. A card supporting
block write shall always be able to accept a block of data defined by WRITE_BL_LEN and its
512bytes derivatives (for example: If write block length=1024bytes then write blocks of 1024 and
512bytes are supported). If WRITE_BL_PARTIAL is allowed (=1) then smaller blocks, up to resolution
of one byte, can be used as well. If the CRC fails, the card shall indicate the failure on the DAT
line (see below); the transferred data will be discarded and not written, and all further transmitted
blocks (in multiple block write mode) will be ignored.

Multiple block write command shall be used rather than continuous single write command to make

512 Bytes.

4.3.3 Data W rite
‧ Block W rite
faster write operation.
If the host uses partial blocks whose accumulated length is not block aligned and block misalign

Date: April 2001

ment is not allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card shall detect the
block misalignment error and abort programming before the beginning of the first misaligned block.
The card shall set the ADDRESS_ERROR error bit in the status register, and while ignoring all further
data transfer, wait in the Receive-data-State for a stop command.

The write operation shall also be aborted if the host tries to write over a write protected area. In this

case, however, the card shall set the WP_VIOLATION bit.
Programming of the CID and CSD registers does not require a previous block length setting. The
transferred data is also CRC protected. If a part of the CSD or CID register is stored in ROM, then
this unchangeable part must match the corresponding part of the receive buffer. If this match fails,
then the card will report an error and not change any register contents.

Some cards may require long and unpredictable times to write a block of data. After receiving a
block of data and completing the CRC check, the card will begin writing and hold the DAT0 line low

if its write buffer is full and unable to accept new data from a new WRITE_BLOCK command. The
host may poll the status of the card with a SEND_STATUS command (CMD13) at any time, and the
card will respond with its status. The status bit READY_FOR_DATA indicates whether the card can
accept new data or whether the write process is still in progress). The host may deselect the card by
issuing CMD7 (to select a different card) which will displace the card into the Disconnect State and
release the DAT line without interrupting the write operation. When reselecting the card, it will reactivate
busy indication by pulling DAT to low if programming is still in progress and the write buffer is
unavailable. Actually, the host may perform simultaneous write operation to several cards with interleaving
process. The interleaving process can be done by accessing each card separately while
other cards are in busy. This process can be done by proper CMD and DAT0-3 line manipulations
(disconnection of busy cards).

‧

tiple Write Blocks operation. Note that The host must send ACMD23 just before WRITE command if
the host wants to use the pre-erase feature. If not, pre-erase-count might be cleared automatically
when another commands (ex: Security Aplication Commands) are executed.

‧ Send Number of W ritten Blocks
Systems that use PipeLine mechanism for data buffers management are, in some cases, unable to
determine which block was the last to be well written to the flash if an error occurs in the middle of a
Multiple Blocks Write operation. The card will respond to ACMD22 with the number of well written

Pre-erase setting prior to a m ultiple block write operation

Setting a number of write blocks to be pre_erased (ACMD23) will make a following Multiple Block
Write operation faster compared to the same operation without preceding ACMD23. The host will
use this command to define how many number of write blocks are going to be send in the next write
operation. If the host will terminate the write operation (Using stop transmission) before all the data
blocks sent to the card the content of the remaining write blocks is undefined(can be either erased
or still have the old data). If the host will send more number of write blocks than defined in ACMD23
the card will erase block one by one(as new data is received). This number will be reset to the
default(=1) value after Multiple Blocks Write operation.
It is recommended using this command preceding CMD25, some of the cards will be faster for Mul

blocks.

4.3.4 Erase
It is desirable to erase many write blocks simultaneously in order to enhance the data throughput.

Date: April 2001

Identification of these write blocks is accomplished with the ERASE_WR_BLK_START(CMD32),

ERASE_WR_BLK_END(CMD33) commands.
The host must adhere to the following command sequence: ERASE_WR_BLK_START,
ERASE_WR_BLK_END and ERASE (CMD38).

If an erase (CMD38) or address setting (CMD32, 33) command is received out of sequence, the

card shall set the ERASE_SEQ_ERROR bit in the status register and reset the whole sequence.
If an out of sequence command (except SEND_STATUS) is received, the card shall set the
ERASE_RESET status bit in the status register, reset the erase sequence and execute the last
command.

If the erase range includes write protected sectors, they shall be left intact and only the non protected
sectors shall be erased. The WP_ERASE_SKIP status bit in the status register shall be set.
The address field in the address setting commands is a write block address in byte units. The card

will ignore all LSB’s below the WRITE_BLK_LEN (see CSD) size.
As described above for block write, the card will indicate that an erase is in progress by holding

DAT0 low. The actual erase time may be quite long, and the host may issue CMD7 to deselect the
card or perform card disconnection, as described in the Block Write section, above.
The data at the card after an erase operation is either ‘0’ or ‘1’, depends on the card vendor.
The SCR register bit DATA_STAT_AFTER_ERASE (bit 55) defines whether it is ‘0’ or ‘1’.

W rite Protect Management

Three write protect methods are supported in the SD Memory Card as follows:

-Mechanical write protect switch (Host responsibility only)
- Card internal write protect (Card’s responsibility)
-Password protection card lock operation.
‧ Mechanical W rite Protect Switch
A mechanical sliding tablet on the side of the card (refer to the mechanical description Chapter 8)
will be used by the user to indicate that a given card is write protected or not. If the sliding tablet is
positioned in such a way that the window is open it means that the card is write protected. If the window
is close the card is not write protected.

A proper, matched, switch on the socket side will indicate to the host that the card is write protected
or not. It is the responsibility of the host to protect the card. The position of the write protect switch is
un-known to the internal circuitry of the card.

‧ Card’s Internal W rite Protection (Optional)
Card data may be protected against either erase or write. The entire card may be permanently write
protected by the manufacturer or content provider by setting the permanent or temporary write protect
bits in the CSD. For cards which support write protection of groups of sectors by setting the
WP_GRP_ENABLE bit in the CSD, portions of the data may be protected (in units of
WP_GRP_SIZE sectors as specified in the CSD), and the write protection may be changed by the
application. The SET_WRITE_PROT command sets the write protection of the addressed write-protect
group, and the CLR_WRITE_PROT command clears the write protection of the addressed

4.3.5

write-protect group.
The SEND_WRITE_PROT command is similar to a single block read command. The card shall

Date: April 2001

send a data block containing 32 write protection bits (representing 32 write protect groups starting at
the specified address) followed by 16 CRC bits. The address field in the write protect commands is
a group address in byte units. The card will ignore all LSB’s below the group size.

The Password Card Lock protection is described in the following section.

4.3.6 Card Lock/Unlock Operation (Optional)
The password protection feature enables the host to lock a card while providing a password, which
later will be used for unlocking the card. The password and its size is kept in an 128 bit PWD and 8
bit PWD_LEN registers, respectively. These registers are non-volatile so that a power cycle will not
erase them.

Locked cards respond to (and execute) all commands in the "basic" command class (class 0),
ACMD41 and “lock card” command class. Thus the host is allowed to reset, initialize, select, query
for status, etc., but not to access data on the card. If the password was previously set (the value of
PWD_LEN is not ‘0’) will be locked automatically after power on.

Similar to the existing CSD and CID register write commands the lock/unlock command is available
in "transfer state" only. This means that it does not include an address argument and the card has to
be selected before using it.

The card lock/unlock command has the structure and bus transaction type of a regular single block
write command. The transferred data block includes all the required information of the command
(password setting mode, PWD itself, card lock/unlock etc.). The following table describes the structure
of the command data block.

Byte # Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 Reserved ERASE LOCK_
UNLOCK
CLR_
PWD
SET_
PWD
1 PWDS_LEN
2
Password data...
PWDS_LEN + 1

Table 6: Lock card data structure

‧ ERASE: ‘1’ Defines Forced Erase Operation (all other bits shall be ‘0’) and only the cmd byte is sent.
‧
LOCK/UNLOCK: ‘1’ = Locks the card. ‘0’ = Unlock the card (note that it is valid to set this bit
together with SET_PWD but it is not allowed to set it together with CLR_PWD).
‧ CLR_PWD: ‘1’ = Clears PWD.
‧ SET_PWD: ‘1’ = Set new password to PWD
‧
PWDS_LEN: Defines the following password/s length (in bytes). In case of Password change,
this field include the total password lengths of old and new passwords.
‧
PWD: In case of set new password contains the new password. In case of password change it
contains the old password followed by new password. All other commands it
contains the current password.
The data block size shall be defined by the host before it sends the card lock/unlock command. This
will allow different password sizes.
The following paragraphs define the various lock/unlock command sequences:

Date: April 2001

‧ Setting the Password
‧
Select a card (CMD7), if not previously selected already
‧
Define the block length (CMD16), given by the 8bit card lock/unlock mode, the 8 bits password
size (in bytes), and the number of bytes of the new password. In case that a password
replacement is done, then the block size shall consider that both passwords, the old
and the new one, are sent with the command.
‧
Send Card Lock/Unlock command with the appropriate data block size on the data line
including 16 bit CRC. The data block shall indicate the mode (SET_PWD), the length
(PWDS_LEN) and the password itself. In case that a password replacement is done, then
the length value (PWDS_LEN) shall include both passwords, the old and the new one, and
the PWD field shall include the old password (currently used) followed by the new password.
Note that card shall handle internally the calculation of the new password length by
subscribing the old password length from PWDS_LEN field.
‧
In case that the sent old password is not correct (not equal in size and content) then
LOCK_UNLOCK_FAILED error bit will be set in the status register and the old password
does not change. In case that PWD matches the sent old password then the given new
password and its size will be saved in the PWD and PWDS_LEN fields, respectively.

Note that the password length register (PWD_LEN) indicates if a password is currently set. When it
equals ‘0’ there is no password set. If the value of PWD_LEN is not equal to zero the card will lock
itself after power up. It is possible to lock the card immediately in the current power session by setting
the LOCK/UNLOCK bit (while setting the password) or sending additional command for card

‧ Reset the Password:
‧
‧

‧

‧
Define the block length (CMD16), given by the 8 bit card lock/unlock mode, the 8 bit password
size (in bytes), and the number of bytes of the currently used password.
‧
Send the card lock/unlock command with the appropriate data block size on the data line
including 16 bit CRC. The data block shall indicate the mode LOCK, the length
(PWDS_LEN) and the password (PWD) itself .
If the PWD content equals to the sent password then the card will be locked and the card-locked
in the status register. If the password is not correct then

LOCK_UNLOCK_FAILED error bit will be set in the status register.
Note that it is possible to set the password and to lock the card in the same sequence. In such case
the host shall perform all the required steps for setting the password (as described above) including
the bit LOCK set while the new password command is sent.

Select a card (CMD7), if not previously selected already
Define the block length (CMD16), given by the 8 bit card lock/unlock mode, the 8 bit password
size (in bytes), and the number of bytes of the currently used password.
Send the card lock/unlock command with the appropriate data block size on the data line
including 16 bit CRC. The data block shall indicate the mode CLR_PWD, the length
(PWDS_LEN) and the password (PWD) itself (LOCK/UNLOCK bit is don’t care). If the
PWD and PWD_LEN content match the sent password and its size, then the content of the
PWD register is cleared and PWD_LEN is set to 0. If the password is not correct then the
LOCK_UNLOCK_FAILED error bit will be set in the status register.

Select a card (CMD7), if not previously selected already

lock.

‧ Locking a card:
status

bit will be

set

If the password was previously set (PWD_LEN is not ‘0’), then the card will be locked automatically
after power on reset.

Date: April 2001

An attempt to lock a locked card or to lock a card that does not have a password will fail and the
LOCK_UNLOCK_FAILED error bit will be set in the status register.

‧ Unlocking the card:
‧
Select a card (CMD7), if not previously selected already.
‧
Define the block length (CMD16), given by the 8 bit card lock/unlock mode, the 8 bit password
size (in bytes), and the number of bytes of the currently used password.
‧
Send the card lock/unlock command with the appropriate data block size on the data line
including 16 bit CRC. The data block shall indicate the mode UNLOCK, the length
(PWDS_LEN) and the password (PWD) itself.
If the PWD content equals to the sent password then the card will be unlocked and the card-locked
status bit will be cleared in the status register. If the password is not correct then the
LOCK_UNLOCK_FAILED error bit will be set in the status register.

Note that the unlocking is done only for the current power session. As long as the PWD is not
cleared the card will be locked automatically on the next power up. The only way to unlock the card
is by clearing the password.

An attempt to unlock an unlocked card will fail and LOCK_UNLOCK_FAILED error bit will be set in

In case that the user forgot the password (the PWD content) it is possible to erase all the card data

Detailed description of the Copyrights Protection mechanism and the related security SD Memory
Card commands can be found in “SD Memory Card Security Specification” document. All the SD
Memory Card security related commands shall be operated in data transfer mode of operation.

As defined in the SDMI spec the data content that is saved in the card is saved already encrypted
and it pass transparently to/from the card. NO operation is done on the data and there is no restriction
to read the data at any time. Associated to every data packet (song, for example) that is saved
in the un-protected memory there is a special data that shall be saved in a protected memory area.
For any access (any Read or Write or Erase Command) from/to the data in the protected area, an
authentication procedure shall be done between the card and the connected device, either the LCM
(PC for example) or the PD (Portable Device - SD Player for example). After the authentication process
was passed OK, the card is ready to accept or give data from/to the connected device. While

content along with the PWD content. This operation is called Forced Erase.

‧
Select a card (CMD7), if not previously selected already.
‧
Define the block length (CMD16) to 1 byte (8bit card lock/unlock command). Send the card
lock/unlock command with the appropriate data block of one byte on the data line including
16 bit CRC. The data block shall indicate the mode ERASE (the ERASE bit shall be the
If the ERASE bit is not the only bit in the data field then the LOCK_UNLOCK_FAILED error bit will
be set in the status register and the erase request is rejected. If the command was accepted then
ALL THE CARD CONTENT WILL BE ERASED including the PWD and PWD_LEN register content
and the locked card will get unlocked. An attempt to force erase on an unlocked card will fail and
LOCK_UNLOCK_FAILED error bit will be set in the status register.

the status register.

‧ Forcing Erase:
only bit set).

4.3.7

the card is in the secured mode of operation (after the authentication succeeded) the argument and
the associated data that is sent to the card or read from the card are encrypted. At the end of the

Date: April 2001

Read/Write/Erase operation the card gets out automatically of its secured mode.

4.3.8 Application specific commands:
The SD Memory Card is defined to be protocol forward compatible to the MultiMediaCard Standard.
The SD Memory Card system is designed to provide a standard interface for a variety applications
types. In order to keep future compatibility to the MultiMediaCard standard together with new SD
Memory Card specific commands the SD Memory Card use the Application Specific commands feature
to implement its proprietary commands. Following is a description of the APP_CMD and
GEN_CMD as were defined in the MultiMediaCard spec.

‧ Application Specific Command – APP_CMD (CMD55)
This command, when received by the card, will cause the card to interpret the following command

In order to use one of the manufacturer specific ACMD’s the host will:
Send APP_CMD. The response will have the APP_CMD bit (new status bit) set signaling to the
host that ACMD is now expected.
Send the required ACMD. The response will have the APP_CMD bit set, indicating that the
accepted command was interpreted as ACMD. If a non-ACMD is sent then it will be respected
by the card as normal SD Memory Card command and the APP_CMD bit in the Card Status

If a non valid command is sent (neither ACMD nor CMD) then it will be handled as a standard SD

Memory Card illegal command error.
From the SD Memory Card protocol point of view the ACMD numbers will be defined by the manufacturers
with some restrictions. The following ACMD numbers are reserved for the SD Memory
Card proprietary applications and may not be used by any SD Memory Card manufacturer:

ACMD6, ACMD13, ACMD17-25, ACMD38-49, ACMD51.

Command - GEN_CMD (CMD56)

as an application specific command, ACMD. The ACMD has the same structure as of regular Multi-
MediaCard standard commands and it may have the same CMD number. The card will recognize it
as ACMD by the fact that it appears after APP_CMD.

The only effect of the APP_CMD is that if the command index of the, immediately, following command
has an ACMD overloading it, the non standard version will be used. If, as an example, a card
has a definition for ACMD13 but not for ACMD7 then, if received immediately after APP_CMD command,
Command 13 will be interpreted as the non standard ACMD13 but, command 7 as the stan-

The bus transaction of the GEN_CMD is the same as the single block read or write commands
(CMD24 or CMD17). The difference is that the argument denotes the direction of the data transfer
(rather than the address) and the data block is not a memory payload data but has a vendor specific
format and meaning. The card shall be selected (‘tran_state’) before sending CMD56. The data
block size is the BLOCK_LEN that was defined with CMD16. The response to CMD56 will be R1.

Note that there are no reserved data pattern (of the associated data block) for SD Memory Card

dard CMD7.

‧

stays clear.

‧ General
specific applications.

Date: April 2001

4.4 Clock Control
The SD Memory Card bus clock signal can be used by the host to turn the cards into energy saving
mode or to control the data flow (to avoid under-run or over-run conditions) on the bus. The host is
allowed to lower the clock frequency or shut it down. For example, in a case that a host with
512Bytes of data buffer would like to transfer data to a card with 1KByte write blocks. So, in order to
preserve a continuous data transfer, from the cards point of view, the clock to the card shall be
stopped after the first 512Bytes. Then the host will fill it internal buffer with another 512Bytes. After
the second half of the write block is ready in the host, it will continue the data transfer to the card by
re-starting the clock supply. In such a way the card does not recognize any interruptions in the data
transfer.

There are a few restrictions the host must follow:

‧ The bus frequency can be changed at any time (under the restrictions of maximum data transfer
‧

TaisolElectronicsfrequency and the identification frequency defined by the specification document).
En examption to the above is ACMD41(SD_APP_OP_COND). After issuing command ACMD41
the following 1) or 2) procedures shall be done by the host until the card becomes ready.
1) Issue continues clock in frequency range of 100KHz-400KHz.
2) If the host wants to stop the clock, poll busy bit by ACMD41 command at less than 50ms
‧ It is an obvious requirement that the clock must be running for the card to output data or
response tokens. After the last SD Memory Card bus transaction, the host is required, to provide
8 (eight) clock cycles for the card to complete the operation before shutting down the clock. Following
is a list of the various bus transactions:
‧A command with no response. 8 clocks after the host command end bit.
‧A command with response. 8 clocks after the card response end bit.
‧A read data transaction. 8 clocks after the end bit of the last data block.
‧A write data transaction. 8 clocks after the CRC status token.
‧ The host is allowed to shut down the clock of a “busy” card. The card will complete the programming
operation regardless of the host clock. However, the host must provide a clock edge for the
card to turn off its busy signal. Without a clock edge the card (unless previously disconnected by
a deselect command -CMD7) will force the DAT line down, forever.
1st 2nd
100KHz-400KHz clocks
1st
Polling less than 50ms interval
3rd
2nd 3rd
(ACMD41 )
(ACMD41 )
< 50ms < 50ms
CLK
.
CMD
CLK
CMD
intervals.

4.5 Cyclic redundancy codes (CRC)
The CRC is intended for protecting SD Memory Card commands, responses and data transfer

Date: April 2001

CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
against transmission errors on the SD Memory Card bus. One CRC is generated for every command
and checked for every response on the CMD line. For data blocks one CRC per transferred
block is generated. The CRC is generated and checked as described in the following.
‧ CRC7
The CRC7 check is used for all commands, for all responses except type R3, and for the CSD and
CID registers. The CRC7 is a 7-bit value and is computed as follows:
generator polynomial: G(x) = x7 + x3 + 1.
M(x) = (first bit) * xn + (second bit) * xn-1 +...+ (last bit) * x0
CRC[6...0] = Remainder [(M(x) * x7) / G(x)]
The first bit is the most left bit of the corresponding bitstring (of the command, response, CID or
CSD). The degree n of the polynomial is the number of CRC protected bits decreased by one. The
number of bits to be protected is 40 for commands and responses (n = 39), and 120 for the CSD
and CID (n = 119).
‧ CRC16
In case of one DAT line usage (as in MultiMediaCard) than the CRC16 is used for payload protection
in block transfer mode. The CRC check sum is a 16-bit value and is computed as follows:
generator polynomial G(x) = x16 +x12 +x5 +1
M(x) = (first bit) * xn + (second bit)* xn-1 +...+ (last bit) * x0
CRC[15...0] = Remainder [(M(x) * x16) / G(x)]
The first bit is the first data bit of the corresponding block. The degree n of the polynomial denotes
the number of bits of the data block decreased by one (e.g. n = 4095 for a block length of 512
bytes). The generator polynomial G(x) is a standard CCITT polynomial. The code has a minimal distance
d=4 and is used for a payload length of up to 2048 Bytes (n <= 16383).
The same CRC16 method shall be used in single DAT line mode and in wide bus mode.
Figure 17: CRC7 generator/checker
data in
data out
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
against transmission errors on the SD Memory Card bus. One CRC is generated for every command
and checked for every response on the CMD line. For data blocks one CRC per transferred
block is generated. The CRC is generated and checked as described in the following.
‧ CRC7
The CRC7 check is used for all commands, for all responses except type R3, and for the CSD and
CID registers. The CRC7 is a 7-bit value and is computed as follows:
generator polynomial: G(x) = x7 + x3 + 1.
M(x) = (first bit) * xn + (second bit) * xn-1 +...+ (last bit) * x0
CRC[6...0] = Remainder [(M(x) * x7) / G(x)]
The first bit is the most left bit of the corresponding bitstring (of the command, response, CID or
CSD). The degree n of the polynomial is the number of CRC protected bits decreased by one. The
number of bits to be protected is 40 for commands and responses (n = 39), and 120 for the CSD
and CID (n = 119).
‧ CRC16
In case of one DAT line usage (as in MultiMediaCard) than the CRC16 is used for payload protection
in block transfer mode. The CRC check sum is a 16-bit value and is computed as follows:
generator polynomial G(x) = x16 +x12 +x5 +1
M(x) = (first bit) * xn + (second bit)* xn-1 +...+ (last bit) * x0
CRC[15...0] = Remainder [(M(x) * x16) / G(x)]
The first bit is the first data bit of the corresponding block. The degree n of the polynomial denotes
the number of bits of the data block decreased by one (e.g. n = 4095 for a block length of 512
bytes). The generator polynomial G(x) is a standard CCITT polynomial. The code has a minimal distance
d=4 and is used for a payload length of up to 2048 Bytes (n <= 16383).
The same CRC16 method shall be used in single DAT line mode and in wide bus mode.
Figure 17: CRC7 generator/checker
data in
data out
DO NOT COPY (c)2000 (c)2001 by SD Group (MEI,SanDisk,Toshiba)

Date: April 2001

CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
In wide bus mode, the CRC16 is done on each line separately.
4.6 Error Conditions
4.6.1 CRC and Illegal Command
All commands are protected by CRC (cyclic redundancy check) bits. If the addressed card’s CRC
check fails, the card does not respond and the command is not executed. The card does not change
its state, and COM_CRC_ERROR bit is set in the status register.
Similarly, if an illegal command has been received, a card shall not change its state, shall not
response and shall set the ILLEGAL_COMMAND error bit in the status register. Only the non-erroneous
state branches are shown in the state diagrams (see Figure 15 to Figure ). Table 17 contains
a complete state transition description.
There are different kinds of illegal commands:
‧ Commands which belong to classes not supported by the card (e.g. write commands in read only
cards).
‧ Commands not allowed in the current state (e.g. CMD2 in Transfer State).
‧ Commands which are not defined (e.g. CMD5).
4.6.2 Read, W rite and Erase Time-out Conditions
The times after which a time-out condition for read operations occurs are (card independent) either
100 tim es longer than the typical access times for these operations given below or 100m s (the
lower of them ). The times after which a time-out condition for Write/Erase operations occurs are
(card independent) either 100 times longer than the typical program times for these operations
given below or 250m s (the lower of them). A card shall complete the command within this time
Figure 18: CRC16 generator/checker
data in
data out
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
In wide bus mode, the CRC16 is done on each line separately.
4.6 Error Conditions
4.6.1 CRC and Illegal Command
All commands are protected by CRC (cyclic redundancy check) bits. If the addressed card’s CRC
check fails, the card does not respond and the command is not executed. The card does not change
its state, and COM_CRC_ERROR bit is set in the status register.
Similarly, if an illegal command has been received, a card shall not change its state, shall not
response and shall set the ILLEGAL_COMMAND error bit in the status register. Only the non-erroneous
state branches are shown in the state diagrams (see Figure 15 to Figure ). Table 17 contains
a complete state transition description.
There are different kinds of illegal commands:
‧ Commands which belong to classes not supported by the card (e.g. write commands in read only
cards).
‧ Commands not allowed in the current state (e.g. CMD2 in Transfer State).
‧ Commands which are not defined (e.g. CMD5).
4.6.2 Read, W rite and Erase Time-out Conditions
The times after which a time-out condition for read operations occurs are (card independent) either
100 tim es longer than the typical access times for these operations given below or 100m s (the
lower of them ). The times after which a time-out condition for Write/Erase operations occurs are
(card independent) either 100 times longer than the typical program times for these operations
given below or 250m s (the lower of them). A card shall complete the command within this time
Figure 18: CRC16 generator/checker
data in
data out
DO NOT COPY (c)2000 (c)2001 by SD Group (MEI,SanDisk,Toshiba)

Date: April 2001

period, or give up and return an error message. If the host does not get any response with the given
time out it should assume the card is not going to respond anymore and try to recover (e.g. reset the
card, power cycle, reject, etc.). The typical access and program times are defined as follows:

‧ Read
The read access time is defined as the sum of the two times given by the CSD parameters TAAC
and NSAC (see Chapter 4.12). These card parameters define the typical delay between the end bit
of the read command and the start bit of the data block. This number is card dependent and should
be used by the host to calculate throughput and the maximal frequency for stream read.

‧ W rite
The R2W_FACTOR field in the CSD is used to calculate the typical block program time obtained by
multiplying the read access time by this factor. It applies to all write/erase commands (e.g.

‧ Erase
SET(CLEAR)_WRITE_PROTECT, PROGRAM_CSD(CID) and the block write commands).

The duration of an erase command will be (order of magnitude) the number of write blocks
(WRITE_BL) to be erased multiplied by the block write delay.

All commands and responses are sent over the CMD line of the SD Memory Card. The command
transmission always starts with the left bit of the bitstring corresponding to the command codeword.

4.7 Commands
4.7.1 Command Types
There are four kinds of commands defined to control the SD Memory Card:
broadcast commands (bc), no response - The broadcast feature is only if all the CMD lines are
connected together in the host. If they are separated then each card will accept it separately on

broadcast commands with response (bcr)
response from all cards simultaneously - Since there is no Open Drain mode in SD Memory Card
this type of commands shall be used only if all the CMD lines are separated - the command will
be accepted and responded by every card separately.
addressed (point-to-point) commands (ac)
no data transfer on DAT

‧

his turn.

‧

‧ addressed (point-to-point) data transfer commands (adtc)
data transfer on DAT
DO NOT COPY (c)2000 (c)2001 by SD Group (MEI,SanDisk,Toshiba)

Date: April 2001

4.7.2 Command Format
All commands have a fixed code length of 48 bits, needing a transmission time of 2.4 ?s @ 20 MHz

Bit position 47 46 [45:40] [39:8] [7:1] 0
W idth (bits) 1 1 6 32 7 1
Value ‘0’ ‘1’ x x x ‘1’
Description start bit transmission
bit
command index argument CRC7 end bit

Table 7: Command Format

A command always starts with a start bit (always ‘0’), followed by the bit indicating the direction of
transmission (host = ‘1’). The next 6 bits indicate the index of the command, this value being interpreted
as a binary coded number (between 0 and 63). Some commands need an argument (e.g. an
address), which is coded by 32 bits. A value denoted by ‘x’ in the table above indicates this variable
is dependent on the command. All commands are protected by a CRC (see Chapter 7.2 for the definition
of CRC7). Every command codeword is terminated by the end bit (always ‘1’). All commands
and their arguments are listed in Table 9-Table 16.

4.7.3 Command Classes (Redefined for SD Memory Card)
The command set of the SD Memory Card system is divided into several classes (See Table 8).

Each class supports a set of card functionalities.
Class 0, 2, 4, 5 and 8 are mandatory and shall be supported by all SD Memory Cards. The other
classes are optional. The supported Card Command Classes (CCC) are coded as a parameter in
the card specific data (CSD) register of each card, providing the host with information on how to
access the card.

Table 8: Card Command Classes (CCCs)

Date: April 2001

Table 8: Card Command Classes (CCCs)

Note (1): The write related commands are mandatory only for the Writable type of Cards (OTP and R/W).

4.7.4 Detailed Command Description
The following tables define in detail all SD Memory Card bus commands. The responses R1-R3, R6

Card
Command
Class
(CCC)
0 1 2 3 4 5 6 7 8 9-11
Supported
comm ands class
description
basic reserv
ed
block
read
reserv
ed
block
write
erase write
protection
lock
card
application
specific
reserv
edCMD13 Mandatory +
CMD15 Mandatory +
CMD16 Mandatory + +
CMD17 Mandatory +
CMD18 Mandatory +
CMD24 Mandatory(1) +
CMD25 Mandatory(1) +
CMD27 Mandatory(1) +
CMD28 Optional +
CMD29 Optional +
CMD30 Optional +
CMD32 Mandatory(1) +
CMD33 Mandatory(1) +
CMD38 Mandatory(1) +
CMD42 Optional +
CMD55 Mandatory +
CMD56 Mandatory
Taisol+
ACMD6 Mandatory +
ACMD13 Mandatory +
ACMD22 Mandatory(1) +
ACMD23 Mandatory(1) +
ACMD41 Mandatory +
ACMD42 Mandatory +
ACMD51 Mandatory +

Date: April 2001

are defined in Chapter 4.9. The registers CID, CSD and DSR are described in Chapter 5.

CMD
INDEX type argument resp abbreviation command description
CMD0 bc [31:0] stuff bits -GO_IDLE_STATE resets all cards to idle state
CMD1 reserved
CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID asks any card to send the CID numbers
on the CMD line (any card that is
connected to the host will respond)
CMD3 bcr [31:0] stuff bits R6 SEND_RELATIVE_
ADDR
ask the card to publish a new relative
address (RCA)
CMD4 bc [31:16] DSR
[15:0] stuff bits
-SET_DSR programs the DSR of all cards
CMD5 reserved
CMD6 reserved
CMD7 ac [31:16] RCA
[15:0] stuff bits
R1b
(only
from the
selected
card)
TaisolSELECT/
DESELECT_
CARD
command toggles a card between the
stand-by and transfer states or
between the programming and disconnect
states. In both cases the
card is selected by its own relative
address and gets deselected by any
other address; address 0 deselects
all. In case that the RCA equal 0 then
the host may do one of the following:
- Use other RCA number to perform
card deselection.
- Re-send CMD3 to change its RCA
number to other than 0 and then use
CMD7with RCA=0 for card deselection.
ElectronicsCo., Ltd.
CMD8 reserved
CMD9 ac [31:16] RCA
[15:0] stuff bits
R2 SEND_CSD addressed card sends its card-specific
data (CSD) on the CMD line.
CMD10 ac [31:16] RCA
[15:0] stuff bits
R2 SEND_CID addressed card sends its card identification
(CID) on CMD the line.
CMD11 reserved
CMD12 ac [31:0] stuff bits R1b STOP_
TRANSMISSION
forces the card to stop transmission
CMD13 ac [31:16] RCA
[15:0] stuff bits
R1 SEND_STATUS addressed card sends its status
register.
CMD14 reserved
CMD15 ac [31:16] RCA
[15:0] stuff bits
-GO_INACTIVE_
STATE
sets the card to inactive state in order
to protect the card stack against communication
breakdowns.

Table 9: Basic commands (class 0)

Date: April 2001

CMD
INDEX type argument resp abbreviation command description
CMD16 ac [31:0] block
length
R1 SET_BLOCKLEN sets the block length (in bytes) for all
following block commands (read and
write). Default block length is specified
in the CSD. Supported only if Partial
block RD/WR operation are allowed in
CSD.
CMD17 adtc [31:0] data
address
R1 READ_SINGLE_
BLOCK
reads a block of the size selected by
the SET_BLOCKLEN command.1
CMD18 adtc [31:0] data
address
R1 READ_MULTIPLE_
BLOCK
continuously transfers data blocks
from card to host until interrupted by a
STOP_TRANSMISSION command.
CMD19
...
CMD23
reserved

Table 10: Block oriented read commands (class 2)

1)The data transferred must not cross a physical block boundary unless READ_BLK_MISALIGN is set in the CSD.

CMD
INDEX type argument resp abbreviation command description
CMD24 adtc [31:0] data
address
R1 WRITE_BLOCK writes a block of the size selected by
the SET_BLOCKLEN command.1
CMD25 adtc [31:0] data
address
R1 WRITE_MULTIPL
E_BLOCK
continuously writes blocks of data until
a STOP_TRANSMISSION follows.
CMD26 Reserved For Manufacturer
CMD27 adtc [31:0] stuff bits R1 PROGRAM_CSD programming of the programmable
bits of the CSD.

Table 11: Block oriented write commands (class 4)

1)The data transferred must not cross a physical block boundary unless WRITE_BLK_MISALIGN is set in the CSD. In
case that write partial blocks is not supported then the block length=default block length (given in CSD).

CMD
INDEX type argument resp abbreviation command description
CMD28 ac [31:0] data
address
R1b SET_WRITE_PROT if the card has write protection features,
this command sets the write
protection bit of the addressed
group. The properties of write protection
are coded in the card specific
data (WP_GRP_SIZE).
CMD29 ac [31:0] data
address
R1b CLR_WRITE_PROT if the card provides write protection
features, this command clears the
write protection bit of the addressed
group.

Table 12: Block oriented write protection commands (class 6)

Date: April 2001

CMD
INDEX type argument resp abbreviation command descriptionCMD30 adtc [31:0] write
protect data
address
R1 SEND_WRITE_
PROT
if the card provides write protection
features, this command asks the
card to send the status of the write
protection bits. 1
CMD31 reserved

Table 12: Block oriented write protection commands (class 6)

1)32 write protection bits (representing 32 write protect groups starting at the specified address) followed by 16 CRC bits are transferred
in a payload format via the data line. The last (least significant) bit of the protection bits corresponds to the first addressed group. If the
addresses of the last groups are outside the valid range, then the corresponding write protection bits shall be set to zero.

CMD
INDEX type argument resp abbreviation command description
CMD32 ac [31:0] data
address
R1 ERASE_WR_BLK_
START
sets the address of the first write-
block to be erased.
CMD33 ac [31:0] data
address
R1 ERASE_WR_BLK_ENDTaisolsets the address of the last write
block of the continuous range to be
erased.
CMD34
...
CMD37
reserved
CMD38 ac [31:0] stuff
bits
R1b ERASE erases all previously selected write
blocks.
CMD39 reserved
CMD40 Non Valid in SD Memory Card -
Reserved for MultiMediaCard I/O
mode
CMD41 reserved

Table 13: Erase commands (class 5)

CMD
INDEX type argument resp abbreviation command description
CMD42 adtc [31:0] stuff
bits.
R1 LOCK_UNLOCK Used to set/reset the password or
lock/unlock the card. The size of
the data block is set by the
SET_BLOCK_LEN command.
CMD43
...
CMD54
reserved

Table 14: Lock card (class 7)

Date: April 2001

CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
All future reserved commands shall have a codeword length of 48 bits, as well as their responses (if
there are any).
The following table describes all the application specific commands supported/reserved by the SD
Memory Card. All the following ACMDs shall be preceded with APP_CMD command (CMD55).
CMD
INDEX type argument resp abbreviation command description
CMD55 ac [31:16] RCA
[15:0] stuff
bits
R1 APP_CMD Indicates to the card that the next
command is an application specific
command rather than a standard
command
CMD56 adtc [31:1] stuff
bits.
[0]: RD/
WR1
R1 GEN_CMD Used either to transfer a data block
to the card or to get a data block
from the card for general purpose /
application specific commands.
The size of the data block shall be
set by the SET_BLOCK_LEN command.
CMD57
...
CMD59
reserved
CMD60
-63
reserved for manufacturer
Table 15: Application specific commands (class 8)
1) RD/WR: “1” the host gets a block of data from the card.
“0” the host sends block of data to the card.
All the application specific commands (given in Table 15) are supported if Class 8 is allowed (mandatory
in SD Memory Card).
ACMD
INDEX type argument resp abbreviation command description
ACMD6 ac [31:2] stuff bits
[1:0]bus width
R1 SET_BUS_WIDTH Defines the data bus width (’00’=1bit or
’10’=4 bits bus) to be used for data
transfer. The allowed data bus widths
are given in SCR register.
ACMD13 adtc [31:0] stuff bits R1 SD_STATUS Send the SD Memory Card status. The
status fields are given in Table 24.
ACMD17 reserved
ACMD18 --
-
-
Reserved
for SD security applications1
ACMD19
to
ACMD21
reserved
ACMD22 adtc [31:0] stuff bits R1 SEND_NUM_WR_
BLOCKS
Send the number of the written (without
errors) write blocks. Responds with
32bit+CRC data block.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
All future reserved commands shall have a codeword length of 48 bits, as well as their responses (if
there are any).
The following table describes all the application specific commands supported/reserved by the SD
Memory Card. All the following ACMDs shall be preceded with APP_CMD command (CMD55).
CMD
INDEX type argument resp abbreviation command description
CMD55 ac [31:16] RCA
[15:0] stuff
bits
R1 APP_CMD Indicates to the card that the next
command is an application specific
command rather than a standard
command
CMD56 adtc [31:1] stuff
bits.
[0]: RD/
WR1
R1 GEN_CMD Used either to transfer a data block
to the card or to get a data block
from the card for general purpose /
application specific commands.
The size of the data block shall be
set by the SET_BLOCK_LEN command.
CMD57
...
CMD59
reserved
CMD60
-63
reserved for manufacturer
Table 15: Application specific commands (class 8)
1) RD/WR: “1” the host gets a block of data from the card.
“0” the host sends block of data to the card.
All the application specific commands (given in Table 15) are supported if Class 8 is allowed (mandatory
in SD Memory Card).
ACMD
INDEX type argument resp abbreviation command description
ACMD6 ac [31:2] stuff bits
[1:0]bus width
R1 SET_BUS_WIDTH Defines the data bus width (’00’=1bit or
’10’=4 bits bus) to be used for data
transfer. The allowed data bus widths
are given in SCR register.
ACMD13 adtc [31:0] stuff bits R1 SD_STATUS Send the SD Memory Card status. The
status fields are given in Table 24.
ACMD17 reserved
ACMD18 --
-
-
Reserved
for SD security applications1
ACMD19
to
ACMD21
reserved
ACMD22 adtc [31:0] stuff bits R1 SEND_NUM_WR_
BLOCKS
Send the number of the written (without
errors) write blocks. Responds with
32bit+CRC data block.
CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
(1) Refer to “SD Memory Card Security Specification” for detailed explanation about the SD Security Features
(2) Command STOP_TRAN (CMD12) shall be used to stop the transmission in Write Multiple Block whether the pre-erase (ACMD23) feature is used or not.
Table 16: Application Specific Commands used/reserved by SD Memory Card
4.8 Card State Transition Table
Table 17 defines the card state transitions in dependency of the received command.
ACMD23 ac [31:23] stuff
bits
[22:0]Number
of blocks
R1 SET_WR_BLK_
ERASE_COUNT
Set the number of write blocks to be
pre-erased before writing (to be used
for faster Multiple Block WR command).
“1”=default (one wr block)(2).
ACMD24 reserved
ACMD25 --
-
-
Reserved
for SD security applications1
ACMD26 --
-
-
Reserved
for SD security applications1
ACMD38 --
-
-
Reserved
for SD security applications1
ACMD39
to
ACMD40
reserved
ACMD41 bcr [31:0]OCR
without busy
R3 SD_SEND_OP_COND Asks the accessed card to send its
operating condition register (OCR)
content in the response on the CMD
line.
ACMD42 ac [31:1] stuff bits
[0]set_cd
R1 SET_CLR_CARD_
DETECT
Connect[1]/Disconnect[0] the 50KOhm
pull-up resistor on CD/DAT3 (pin 1) of
the card. The pull-up may be used for
card detection.
ACMD43
ACMD49
--
-
-
Reserved
for SD security applications1
ACMD51 adtc [31:0] staff bits R1 SEND_SCR Reads the SD Configuration Register
(SCR).
current state
idle ready ident stby tran data rcv prg dis ina
command changes to
class independent
CRC error ----------
command not supported
----------
class 0
Table 17: Card state transition table
ACMD
INDEX type argument resp abbreviation command description
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
(1) Refer to “SD Memory Card Security Specification” for detailed explanation about the SD Security Features
(2) Command STOP_TRAN (CMD12) shall be used to stop the transmission in Write Multiple Block whether the pre-erase (ACMD23) feature is used or not.
Table 16: Application Specific Commands used/reserved by SD Memory Card
4.8 Card State Transition Table
Table 17 defines the card state transitions in dependency of the received command.
ACMD23 ac [31:23] stuff
bits
[22:0]Number
of blocks
R1 SET_WR_BLK_
ERASE_COUNT
Set the number of write blocks to be
pre-erased before writing (to be used
for faster Multiple Block WR command).
“1”=default (one wr block)(2).
ACMD24 reserved
ACMD25 --
-
-
Reserved
for SD security applications1
ACMD26 --
-
-
Reserved
for SD security applications1
ACMD38 --
-
-
Reserved
for SD security applications1
ACMD39
to
ACMD40
reserved
ACMD41 bcr [31:0]OCR
without busy
R3 SD_SEND_OP_COND Asks the accessed card to send its
operating condition register (OCR)
content in the response on the CMD
line.
ACMD42 ac [31:1] stuff bits
[0]set_cd
R1 SET_CLR_CARD_
DETECT
Connect[1]/Disconnect[0] the 50KOhm
pull-up resistor on CD/DAT3 (pin 1) of
the card. The pull-up may be used for
card detection.
ACMD43
ACMD49
--
-
-
Reserved
for SD security applications1
ACMD51 adtc [31:0] staff bits R1 SEND_SCR Reads the SD Configuration Register
(SCR).
current state
idle ready ident stby tran data rcv prg dis ina
command changes to
class independent
CRC error ----------
command not supported
----------
class 0
Table 17: Card state transition table
ACMD
INDEX type argument resp abbreviation command description
CONFIDENTIAL

SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01 SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description

current state
idle ready ident stby tran data rcv prg dis inaCMD0 idle idle idle idle idle idle idle idle idle -
CMD2 -ident --------
CMD3 --stby stby ------
CMD4 ---stby ------
CMD7, card is
addressed
---tran ----prg -
CMD7, card is not
addressed
---stby stby stby -dis --
CMD9 ---stby ------
CMD10 ---stby ------
CMD12 -----tran prg ---
CMD13 ---stby tran data rcv prg dis -
CMD15 ---ina ina ina ina ina ina -
class 2
TaisolElectronicsCMD16 ----tran -----
CMD17 ----data -----
CMD18 ----data -----
class 4
Co., Ltd.
CMD16 see class 2
CMD24 ----rcv -----
CMD25 ----rcv -----
CMD27 ----rcv -----
class 6
CMD28 ----prg -----
CMD29 ----prg -----
CMD30 ----data -----
class 5
CMD32 ----tran -----
CMD33 ----tran -----
CMD38 ----prg -----
class 7
CMD42 ----rcv -----
class 8
CMD55 idle --stby tran data rcv prg dis -
CMD56; RD/WR = 0 ----rcv -----
CMD56; RD/WR = 1 ----data -----
ACMD6 ----tran -----

Table 17: Card state transition table

Date: April 2001

current state
idle ready ident stby tran data rcv prg dis inaACMD13 ----tran -----
ACMD22 ----tran -----
ACMD23 ----tran -----
ACMD18,25,26,38,
43,44,45,46,47,48,49
Refer to “SD Memory Card Security Specification” for explanation about the SD
Security Features
ACMD41, card VDD
range compatible
ready ---------
ACMD41, card is busy idle ---------
ACMD41, card VDD
range not compatible
ina ---------
ACMD42 ----tran -----
ACMD51 ----data -----
class 9- 11
CMD41;
CMD43...CMD54,
CMD57-CMD59
reserved
CMD60...CMD63 reserved for manufacturer

Table 17: Card state transition table

The state transitions of the SD Memory Card application specific commands are given under Class

All responses are sent via the command line CMD. The response transmission always starts with
the left bit of the bitstring corresponding to the response codeword. The code length depends on the

A response always starts with a start bit (always ‘0’), followed by the bit indicating the direction of
transmission (card = ‘0’). A value denoted by ‘x’ in the tables below indicates a variable entry. All
responses except for the type R3 (see below) are protected by a CRC (see Chapter 7.2 for the definition
of CRC7). Every command codeword is terminated by the end bit (always ‘1’).

There are four types of responses. Their formats are defined as follows:

R1 (normal response command): code length 48 bit. The bits 45:40 indicate the index of the

command to be responded to, this value being interpreted as a binary coded number (between 0

and 63). The status of the card is coded in 32 bits. Note that in case that data transfer to the card

is involved then a busy signal may appear on the data line after the transmission of each block of

data. The host shell check for busy after data block transmission.

8, above.

4.9 Responses
response type.

‧

Date: April 2001

The card status is described in Chapter 4.10.

Bit position 47 46 [45:40] [39:8] [7:1] 0
W idth (bits) 1 1 6 32 7 1
Value ‘0’ ‘0’ x x x ‘1’
Description start bit transmission
bit
command index card status CRC7 end bit

Table 18: Response R1

‧
R1b is identical to R1 with an optional busy signal transmitted on the data line. The card may
become busy after receiving these commands based on its state prior to the command reception.
The Host shell check for busy at the response. Refer to Chapter 4.12.3 for detailed description
and timing diagrams.
‧
R2 (CID, CSD register): code length 136 bits. The contents of the CID register are sent as a
response to the commands CMD2 and CMD10. The contents of the CSD register are sent as a
response to CMD9. Only the bits [127...1] of the CID and CSD are transferred, the reserved bit
[0] of these registers is replaced by the end bit of the response.
Bit position 135 134 [133:128] [127:1] 0
W idth (bits) 1 1 6 127 1
Value ‘0’ ‘0’ ‘111111’ x ‘1’
Description start bit transmission
bit
reserved CID or CSD register incl.
internal CRC7
end bit

Table 19: Response R2

‧
R3 (OCR register): code length 48 bits. The contents of the OCR register is sent as a response
to ACMD41.
Bit position 47 46 [45:40] [39:8] [7:1] 0
W idth (bits) 1 1 6 32 7 1
Value ‘0’ ‘0’ ‘111111’ x ‘1111111’ ‘1’
Description start bit transmission
bit
reserved OCR register reserved end bit

Table 20: Response R3

Date: April 2001

‧ R6 (Published RCA response): code length 48 bit. The bits 45:40 indicate the index of the
Bit position 47 46 [45:40] [39:8]
Argument field [7:1] 0
W idth (bits) 1 1 6 16 16 7 1
Value ‘0’ ‘0’ x x x x ‘1’
Description start bit transmission
bit
command
index
(‘000011’)
New
published
RCA [31:16]
of the card
[15:0] card
status bits:
23,22,19,12:0
(see Table 22)
CRC7 end bit

Table 21: Response R6

command to be responded to - in that case it will be ‘000011’ (together with bit 5 in the status bits it
means = CMD3). The 16 MSB bits of the argument field are used for the Published RCA number.

SD Memory Card Status

SD Memory Card supports two card status field as follows:

: Extended status field of 512bits that supports special features of the SD Memory
Card and future Application Specific features.

The response format R1 contains a 32-bit field named card status. This field is intended to transmit
the card’s status information (which may be stored in a local status register) to the host. If not specified
otherwise, the status entries are always related to the previous issued command. The semantics
of this register is according to the CSD entry SPEC_VERS (see Chapter 5.3), indicating the

‧ R: Detected and set for the actual command response.
‧ X: Detected and set during command execution. The host must poll the card by issuing the status
command in order to read these bits.
‧ A: According to the card current state.
‧ B: Always related to the previous command. Reception of a valid command will clear it (with a
version of the response formats (possibly used for later extensions).
Table 22 defines the different entries of the status. The type and clear condition fields in the table
are abbreviated as follows:

4.10

-‘Card Status’: compatible to the MultiMediaCard protocol.
‘SD_Status’

4.10.1 Card Status
‧ Type:
‧ E: Error bit.
‧ S: Status bit.
‧ Clear Condition:
delay of one command).

‧ C: Clear by read
DO NOT COPY (c)2000 (c)2001 by SD Group (MEI,SanDisk,Toshiba)

Date: April 2001

Bits Identifier Type Value Description
Clear
Cond
ition
31 OUT_OF_RANGE E R X ’0’= no error
’1’= error
The command’s argument was out
of the allowed range for this card.
C
30 ADDRESS_ERROR E R ’0’= no error
’1’= error
A misaligned address which did
not match the block length was
used in the command.
C
29 BLOCK_LEN_ERROR E R ’0’= no error
’1’= error
The transferred block length is not
allowed for this card, or the number
of transferred bytes does not
match the block length.
C
28 ERASE_SEQ_ERROR E R ’0’= no error
’1’= error
An error in the sequence of erase
commands occurred.
C
27 ERASE_PARAM E R X ’0’= no error
’1’= error
An invalid selection of write-blocks
for erase occurred.
C
26 WP_VIOLATION E R X ’0’= not protected
’1’= protected
Attempt to program a write protected
block.
C
25 CARD_IS_LOCKED S X ‘0’ = card
unlocked
‘1’ = card locked
When set, signals that the card is
locked by the host
A
24 LOCK_UNLOCK_FAIL
ED
E R X ‘0’ = no error
‘1’ = error TaisolElectronicsCo., Ltd.Set when a sequence or password
error has been detected in lock/
unlock card command or if there
was an attempt to access a locked
card
C
23 COM_CRC_ERROR E R ’0’= no error
’1’= error
The CRC check of the previous
command failed.
B
22 ILLEGAL_COMMAND E R ’0’= no error
’1’= error
Command not legal for the card
state
B
21 CARD_ECC_FAILED E R X ’0’= success
’1’= failure
Card internal ECC was applied but
failed to correct the data.
C
20 CC_ERROR E R X ’0’= no error
’1’= error
Internal card controller error C
19 ERROR E R X ’0’= no error
’1’= error
A general or an unknown error
occurred during the operation.
C
18 reserved
17 reserved

Table 22: Card status

Date: April 2001

Bits Identifier Type Value Description
Clear
Cond
ition16 CID/
CSD_OVERWRITE
E R X ’0’= no error
’1’= error
can be either one of the following
errors:
- The CID register has been
already written and can not be
overwritten
- The read only section of the
CSD does not match the card
content.
- An attempt to reverse the copy
(set as original) or permanent
WP (unprotected) bits was
made.
C
15 WP_ERASE_SKIP S X ’0’= not protected
’1’= protected
Only partial address space was
erased due to existing write protected
blocks.
C
14 CARD_ECC_DISABLE
D
S X ’0’= enabled
’1’= disabled
The command has been executed
without using the internal ECC.
A
13 ERASE_RESET S R ’0’= cleared
’1’= set
An erase sequence was cleared
before executing because an out
of erase sequence command was
received
C
12:9 CURRENT_STATE S X 0 = idle
1 = ready
2 = ident
3 = stby
4 = tran
5 = data
6 = rcv
7 = prg
8 = dis
9-15 = reservedTaisolElectronicsCo., Ltd.The state of the card when receiving
the command. If the
command execution causes a
state change, it will be visible to
the host in the response to the
next command.
The four bits are interpreted as a
binary coded number between 0
and 15.
B
8 READY_FOR_DATA S X ’0’= not ready
’1’= ready
corresponds to buffer empty signalling
on the bus
A
7:6
5 APP_CMD S R ‘0’ = Disabled
‘1’ = Enabled
The card will expect ACMD, or
indication that the command has
been interpreted as ACMD
C
4 reserved
3 AKE_SEQ_ERROR
(SD Memory Card app.
spec.)
E R ‘0’ = no error
‘1’ = error
Error in the sequence of authentication
process
C
2 reserved for application specific commands
1, 0 reserved for manufacturer test mode

Table 22: Card status

The following table defines for each command responded by a R1 response the affected bits in the

Date: April 2001

CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
status field. An ‘x’ means the error/status bit may be set in the response to the respective command.
4.10.2 SD Status
The SD Status contains status bits that are related to the SD Memory Card proprietary features and
may be used for future application specific usage. The size of the SD Status is one data block of
512bit. The content of this register is transmitted to the Host over the DAT bus along with 16 bit
CRC. The SD Status is sent to the host over the DAT bus if ACMD13 is sent (CMD55 followed with
CMD13). ACMD13 can be sent to a card only in ‘tran_state’(card is selected). SD Status structure
CMD#
Response Format 1 Status bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12:9 8 5
3(1) x x x x
7 x x x x x x x x x x x x x x x x x
12 x x x x x x x x x x x x x
13 x x x x x x x x x x x x x x x x x x
16 x x x x x x x x x x x x x x x x x
17 x x x x x x x x x x x x x x x x x x
18 x x x x x x x x x x x x x x x x x x
24 x x x x x x x x x x x x x x x x x x x
25 x x x x x x x x x x x x x x x x x x x
26 x x x x x x x x x x x x x x x x
27 x x x x x x x x x x x x x x x x
28 x x x x x x x x x x x x x x x x x
29 x x x x x x x x x x x x x x x x x
30 x x x x x x x x x x x x x x x x x
32 x x x x x x x x x x x x x x x x x x
33 x x x x x x x x x x x x x x x x x x
38 x x x x x x x x x x x x x x x x x
42 x x x x x x x x x x x x x x x x
55 x x x x x x x x x x x x x x x x x
56 x x x x x x x x x x x x x x x x x x
ACMD6 x x x x x x x x x x x x x x x x x x
ACMD13 x x x x x x x x x x x x x x x x x
ACMD22 x x x x x x x x x x x x x x x x x
ACMD23 x x x x x x x x x x x x x x x x x
ACMD42 x x x x x x x x x x x x x x x x x
ACMD51 x x x x x x x x x x x x x x x x x
Table 23: Card status field / command - cross reference
(1) The response to CMD3 is R6 that includes only bits 23, 22, 19 and 12:9 out of the Card Status
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
status field. An ‘x’ means the error/status bit may be set in the response to the respective command.
4.10.2 SD Status
The SD Status contains status bits that are related to the SD Memory Card proprietary features and
may be used for future application specific usage. The size of the SD Status is one data block of
512bit. The content of this register is transmitted to the Host over the DAT bus along with 16 bit
CRC. The SD Status is sent to the host over the DAT bus if ACMD13 is sent (CMD55 followed with
CMD13). ACMD13 can be sent to a card only in ‘tran_state’(card is selected). SD Status structure
CMD#
Response Format 1 Status bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12:9 8 5
3(1) x x x x
7 x x x x x x x x x x x x x x x x x
12 x x x x x x x x x x x x x
13 x x x x x x x x x x x x x x x x x x
16 x x x x x x x x x x x x x x x x x
17 x x x x x x x x x x x x x x x x x x
18 x x x x x x x x x x x x x x x x x x
24 x x x x x x x x x x x x x x x x x x x
25 x x x x x x x x x x x x x x x x x x x
26 x x x x x x x x x x x x x x x x
27 x x x x x x x x x x x x x x x x
28 x x x x x x x x x x x x x x x x x
29 x x x x x x x x x x x x x x x x x
30 x x x x x x x x x x x x x x x x x
32 x x x x x x x x x x x x x x x x x x
33 x x x x x x x x x x x x x x x x x x
38 x x x x x x x x x x x x x x x x x
42 x x x x x x x x x x x x x x x x
55 x x x x x x x x x x x x x x x x x
56 x x x x x x x x x x x x x x x x x x
ACMD6 x x x x x x x x x x x x x x x x x x
ACMD13 x x x x x x x x x x x x x x x x x
ACMD22 x x x x x x x x x x x x x x x x x
ACMD23 x x x x x x x x x x x x x x x x x
ACMD42 x x x x x x x x x x x x x x x x x
ACMD51 x x x x x x x x x x x x x x x x x
Table 23: Card status field / command - cross reference
(1) The response to CMD3 is R6 that includes only bits 23, 22, 19 and 12:9 out of the Card Status
CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
is described in bellow.
The same abbreviation for ‘type’ and ‘clear condition’ were used as for the Card Status above.
Table 24: SD Card Status
4.11 M emory Array Partitioning
The basic unit of data transfer to/from the SD Memory Card is one byte. All data transfer operations
which require a block size always define block lengths as integer multiples of bytes. Some special
functions need other partition granularity.
For block oriented commands, the following definition is used:
‧ Block: is the unit which is related to the block oriented read and write commands. Its size is the
number of bytes which will be transferred when one block command is sent by the host. The size
of a block is either programmable or fixed. The information about allowed block sizes and the
programmability is stored in the CSD.
For devices which have erasable memory cells, special erase commands are defined. The granularity
of the erasable units is in general not the same as for the block oriented commands:
Bits Identifier Type Value Description
Clear
Cond
ition
511:
510
DAT_BUS_WIDTH S R ’00’= 1 (default)
‘01’= reserved
‘10’= 4 bit width
‘11’= reserved
Shows the currently defined data
bus width that was defined by
SET_BUS_WIDTH command
A
509 SECURED_MODE S R ’0’= Not in the mode
’1’= In Secured Mode
Card is in Secured Mode of operation
(refer to “SD Security Specification”).
A
508:
496
reserved
495:
480
SD_CARD_TYPE SR ’00xxh’= SD Memory
Cards as defined in
Physical Spec Ver.1
(’x’=don’t care).
The following cards
are currently defined:
’0000’= Regular SD
RD/WR Card.
’0001’= SD ROM Card
In the future the 8LSBs will be used
to define different variations of a SD
Memory Card (Each bit will define
different SD Type). The 8MSBs will
be used to define SD Cards that do
not comply with SD Memory Card as
was defined in Spec Ver.1
A
479:
448
SIZE_OF_PROTE
CTED_AREA
SR Size of protected area
(in units of
MULT*BLOCK_LEN
refer to CSD register
Table 5.3)
Shows the size of protected area.
The actual area =
(SIZE_OF_PROTECTED_AREA) *
MULT * BLOCK_LEN.
A
447:
312
reserved
311:
0
reserved for manufacturer
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
is described in bellow.
The same abbreviation for ‘type’ and ‘clear condition’ were used as for the Card Status above.
Table 24: SD Card Status
4.11 M emory Array Partitioning
The basic unit of data transfer to/from the SD Memory Card is one byte. All data transfer operations
which require a block size always define block lengths as integer multiples of bytes. Some special
functions need other partition granularity.
For block oriented commands, the following definition is used:
‧ Block: is the unit which is related to the block oriented read and write commands. Its size is the
number of bytes which will be transferred when one block command is sent by the host. The size
of a block is either programmable or fixed. The information about allowed block sizes and the
programmability is stored in the CSD.
For devices which have erasable memory cells, special erase commands are defined. The granularity
of the erasable units is in general not the same as for the block oriented commands:
Bits Identifier Type Value Description
Clear
Cond
ition
511:
510
DAT_BUS_WIDTH S R ’00’= 1 (default)
‘01’= reserved
‘10’= 4 bit width
‘11’= reserved
Shows the currently defined data
bus width that was defined by
SET_BUS_WIDTH command
A
509 SECURED_MODE S R ’0’= Not in the mode
’1’= In Secured Mode
Card is in Secured Mode of operation
(refer to “SD Security Specification”).
A
508:
496
reserved
495:
480
SD_CARD_TYPE SR ’00xxh’= SD Memory
Cards as defined in
Physical Spec Ver.1
(’x’=don’t care).
The following cards
are currently defined:
’0000’= Regular SD
RD/WR Card.
’0001’= SD ROM Card
In the future the 8LSBs will be used
to define different variations of a SD
Memory Card (Each bit will define
different SD Type). The 8MSBs will
be used to define SD Cards that do
not comply with SD Memory Card as
was defined in Spec Ver.1
A
479:
448
SIZE_OF_PROTE
CTED_AREA
SR Size of protected area
(in units of
MULT*BLOCK_LEN
refer to CSD register
Table 5.3)
Shows the size of protected area.
The actual area =
(SIZE_OF_PROTECTED_AREA) *
MULT * BLOCK_LEN.
A
447:
312
reserved
311:
0
reserved for manufacturer
CONFIDENTIAL

ElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
‧ Sector: is the unit which is related to the erase commands. Its size is the number of blocks which
will be erased in one portion. The size of a sector is fixed for each device. The information about
the sector size (in blocks) is stored in the CSD.
For devices which include a write protection:
‧ WP-Group: is the minimal unit which may have individual write protection. Its size is the number
of groups which will be write protected by one bit. The size of a WP-group is fixed for each
device. The information about the size is stored in the CSD.
Figure 19: W rite Protection hierarchy
Each WP-group may have an additional write protection bit. The write protection bits are programmable
via special commands (see Chapter 4.7.4).
Both functions are optional and only useful for writable/erasable devices. The write protection may
also be useful for multi type cards (e.g. a ROM - Flash combination). The information about the
availability is stored in the CSD.
SD Memory Card
Sector 3
Sector n
WP Group 0
W P Group 1
WP Group n
Sector 2
Block 0 Block 1 Block 2 Block n
Sector 1
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
‧ Sector: is the unit which is related to the erase commands. Its size is the number of blocks which
will be erased in one portion. The size of a sector is fixed for each device. The information about
the sector size (in blocks) is stored in the CSD.
For devices which include a write protection:
‧ WP-Group: is the minimal unit which may have individual write protection. Its size is the number
of groups which will be write protected by one bit. The size of a WP-group is fixed for each
device. The information about the size is stored in the CSD.
Figure 19: W rite Protection hierarchy
Each WP-group may have an additional write protection bit. The write protection bits are programmable
via special commands (see Chapter 4.7.4).
Both functions are optional and only useful for writable/erasable devices. The write protection may
also be useful for multi type cards (e.g. a ROM - Flash combination). The information about the
availability is stored in the CSD.
SD Memory Card
Sector 3
Sector n
WP Group 0
W P Group 1
WP Group n
Sector 2
Block 0 Block 1 Block 2 Block n
Sector 1
DO NOT COPY (c)2000 (c)2001 by SD Group (MEI,SanDisk,Toshiba)

Date: April 2001

4.12 Timings
All timing diagrams use the following schematics and abbreviations:

S Start bit (= ‘0’)
T Transmitter bit (Host = ‘1’, Card = ‘0’)
P One-cycle pull-up (= ‘1’)
E End bit (=1)
Z High impedance state (-> = ‘1’)
D Data bits
X Don’t Care data bits (from card)
* Repetition
CRC Cyclic redundancy check bits (7 bits)
Card active
Host active

TaisolCo., Ltd.
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card
respectively host output driver, while Z-bit is driven to (respectively kept) HIGH by the pull-up resistors
RCMD respectively RDAT. Actively-driven P-bits are less sensitive to noise.
All timing values are defined in Table 26.
4.12.1 Command and Response
Both host command and card response are clocked out with the rising edge of the host clock.
‧ Card identification and card operation conditions timing
The timing for CMD2 and ACMD41 is given bellow. The command is followed by a period of two Z
bits (allowing time for direction switching on the bus) and then by P bits pushed up by the responding
card. The card response to the host command starts after NID clock cycles.
Figure 20: Identification tim ing (card identification mode)
‧ Assign a card relative address
The SEND_RELATIVE_ADDR (CMD 3) for SD Memory Card timing is given bellow. Note that
CMD3 command’s content, functionality and timing are different for MultiMediaCard. The minimum
delay between the host command and card response is NCR clock cycles.
Table 25: Tim ing diagram symbols
<------Host command ----> <-NID cycles -> <---- CID or OCR --->
S T content CRC E Z Z P * * * P S T content Z Z Z
CMD

Date: April 2001

CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
Figure 21: SEND_RELATIVE_ADDR timing
‧ Data transfer m ode.
After the card published it own RCA it will switch to data transfer mode. The command is followed by
a period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up
by the responding card. This timing diagram is relevant for all responded host commands except
and ACMD41 and CMD2:
Figure 22: Command response timing (data transfer mode)
‧ Last Card Response - Next Host Comm and Timing
After receiving the last card response, the host can start the next command transmission after at
least NRC clock cycles. This timing is relevant for any host command.
Figure 23: Tim ing response end to next CMD start (data transfer mode)
‧ Last Host Command - Next Host Comm and Tim ing
After the last command has been sent, the host can continue sending the next command after at
least NCC clock periods.
Figure 24: Tim ing of command sequences (all modes)
4.12.2 Data Read
* Note: DAT line represents data bus (either 1 or 4 bits).
‧ Single Block Read
The host selects one card for data read operation by CMD7, and sets the valid block length for block
oriented data transfer by CMD16. The basic bus timing for a read operation is given in Figure 25.
The sequence starts with a single block read command (CMD17) which specifies the start address
<---- Host command ----> <-NCR cycles -><-------- Response --------->
CMD S T content CRC E Z Z P * * * P S T content CRC E Z Z Z
<---- Host command ----> <-NCR cycles -><-------- Response --------->
CMD S T content CRC E Z Z P * * * P S T content CRC E Z Z Z
<-------- Response --------> <-NRC cycles -> <---- Host command ----->
CMD S T content CRC E Z * * * * * * Z S T content CRC E
<----- Host command ----> <-NCC cycles -> <---- Host command ----->
CMD S T content CRC E Z * * * * * * Z S T content CRC E
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
Figure 21: SEND_RELATIVE_ADDR timing
‧ Data transfer m ode.
After the card published it own RCA it will switch to data transfer mode. The command is followed by
a period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up
by the responding card. This timing diagram is relevant for all responded host commands except
and ACMD41 and CMD2:
Figure 22: Command response timing (data transfer mode)
‧ Last Card Response - Next Host Comm and Timing
After receiving the last card response, the host can start the next command transmission after at
least NRC clock cycles. This timing is relevant for any host command.
Figure 23: Tim ing response end to next CMD start (data transfer mode)
‧ Last Host Command - Next Host Comm and Tim ing
After the last command has been sent, the host can continue sending the next command after at
least NCC clock periods.
Figure 24: Tim ing of command sequences (all modes)
4.12.2 Data Read
* Note: DAT line represents data bus (either 1 or 4 bits).
‧ Single Block Read
The host selects one card for data read operation by CMD7, and sets the valid block length for block
oriented data transfer by CMD16. The basic bus timing for a read operation is given in Figure 25.
The sequence starts with a single block read command (CMD17) which specifies the start address
<---- Host command ----> <-NCR cycles -><-------- Response --------->
CMD S T content CRC E Z Z P * * * P S T content CRC E Z Z Z
<---- Host command ----> <-NCR cycles -><-------- Response --------->
CMD S T content CRC E Z Z P * * * P S T content CRC E Z Z Z
<-------- Response --------> <-NRC cycles -> <---- Host command ----->
CMD S T content CRC E Z * * * * * * Z S T content CRC E
<----- Host command ----> <-NCC cycles -> <---- Host command ----->
CMD S T content CRC E Z * * * * * * Z S T content CRC E
DO NOT COPY (c)2000 (c)2001 by SD Group (MEI,SanDisk,Toshiba)

Date: April 2001

CONFIDENTIAL

<-
Host command ---> <-NCR cycles-> <---- Response ------>
T content CRC E Z Z P * P S T content CRC E Z Z P P P P P P P P P P P P P
<--
NAC cycles ----> <-- Read Data --> <-NAC
cycles --><-Read Data ->
Z Z * * * * Z Z Z Z Z Z P * * * * * * * P S content CRC E P * * * * * * * P S D D D D D

SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description

in the argument field. The response is sent on the CMD line as usual.

<----- Host command -----> <-NCR cycles -><-------- Response --------->
CMD S T content CRC E Z Z P * * * P S T content CRC E
<-------- NAC cycles -------> <- Read Data
DAT Z Z Z * * * * Z Z Z Z Z Z P * * * * * * * * * * P S D D D * * *
Figure 25: Tim ing of single block read

Data transmission from the card starts after the access time delay NAC beginning from the end bit of
the read command. After the last data bit, the CRC check bits are suffixed to allow the host to check
for transmission errors.

‧ Multiple Block Read
In multiple block read mode, the card sends a continuous flow of data blocks following the initial
host read command. The data flow is terminated by a stop transmission command (CMD12).
Figure 26 describes the timing of the data blocks and Figure 27 the response to a stop command.
The data transmission stops two clock cycles after the end bit of the stop command.

CMD S

DAT Z

Figure 27: Timing of stop command (CMD12, data transfer mode)

4.12.3 Data W rite
‧ Single Block W rite
The host selects one card for data write operation by CMD7.
The host sets the valid block length for block oriented data transfer by CMD16.
The basic bus timing for a write operation is given in Figure 28. The sequence starts with a single

block write command (CMD24) which determines (in the argument field) the start address. It is
responded by the card on the CMD line as usual. The data transfer from the host starts NWR clock
cycles after the card response was received.

The data is suffixed with CRC check bits to allow the card to check it for transmission errors. The
card sends back the CRC check result as a CRC status token on the DAT0 line. In the case of transmission
error the card sends a negative CRC status (‘101’). In the case of non erroneous transmission
the card sends a positive CRC status (‘010’) and starts the data programming procedure.

Figure 26: Timing of multiple block read command

CMD
DAT

<----- Host command -----> <-NCR cycles -><-------- Response --------->
S T content CRC E Z Z P * * * P S T content CRC E
D D D * * * * * * * * D D D E Z Z * * * * * * * * * * * * * * * * * * * *

Date: April 2001

When a flash programming error occurs the card will ignore all further data blocks. In this case no
CRC response will be sent to the host and, therefore, there will not be CRC start bit on the bus and
the three CRC status bits will read (‘111‘).

<-Host cmnd->
CMD

DAT0
DAT1-3

<- NCR -> <-Card response >
E Z Z P * P S T Content CRC E Z Z P * * * * * * * * * * * * * * * * * * P P P P P P P P
<-NWR-> <- Write data -> CRC status <- Busy ->
Z Z * * * * * * Z Z Z * * * Z Z Z Z P * P S content CRC E Z Z S Status E S L * L E Z
Z Z * * * * * * Z Z Z * * * Z Z Z Z P * P S content CRC E Z Z X X X X X X X X X Z

Figure 28: Timing of the block write command

Note that the CRC response output is always two clocks after the end of data.
If the card does not have a free data receive buffer, the card indicates this condition by pulling down
the data line to LOW. The card stops pulling down the DAT0 line as soon as at least one receive
buffer for the defined data transfer block length becomes free. This signalling does not give any

Data+CRC

Figure 29: Timing of the multiple block write command

The stop transmission command works similar as in the read mode. Figure 30 to Figure 33 describe

information about the data write status which must be polled by the host.

Multiple Block W rite

In multiple block write mode, the card expects continuous flow of data blocks following the initial

As in the case of single block write, the data is suffixed with CRC check bits to allow the card to
check it for transmission errors. The card sends back the CRC check result as a CRC status token
on the DAT0 line. In the case of transmission error the card sends a negative CRC status (‘101’). In
the case of non erroneous transmission the card sends a positive CRC status (‘010’) and starts the
data programming procedure. When a flash programming error occurs the card will ignore all further
data blocks. In this case no CRC response will be sent to the host and, therefore, there will not be
CRC start bit on the bus and the three CRC status bits will read (‘111‘);

The data flow is terminated by a stop transmission command (CMD12). Figure 29 describes the timing
of the data blocks with and without card busy signal.

* * * * * * * * * * * * * * * * * *

P
<- Write data ->

<-NWR->

CRC status

<- Write data ->

CRC status

<- Busy ->

<-NWR->
Status Status

Data+CRC

P * P

L * L

P * P

‧

host write command.

<-CardRsp->

CMD

<-NWR->

DAT

P * P

Date: April 2001

CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
the timing of the stop command in different card states.
Figure 30: Stop transm ission during data transfer from the host
The card will treat a data block as successfully received and ready for programming only if the CRC
data of the block was validated and the CRC status token sent back to the host. Figure 31 is an
example of an interrupted (by a host stop command) attempt to transmit the CRC status block. The
sequence is identical to all other stop transmission examples. The end bit of the host command is
followed, on the data line, with one more data bit and start of busy signalling. In that case there are
no Z clocks, for switching the bus direction, because the bus direction is already towards the host.
The received data block, in this case is considered incomplete and will not be programmed.
Figure 31: Stop transm ission during CRC status transfer from the card
All previous examples dealt with the scenario of the host stopping the data transmission during an
active data transfer. The following two diagrams describe a scenario of receiving the stop transmission
between data blocks. In the first example the card is busy programming the last block while in
the second the card is idle. However, there are still unprogrammed data blocks in the input buffers.
These blocks are being programmed as soon as the stop transmission command is received and
the card activates the busy signal.
Figure 32: Stop transm ission received after last data block. Card is busy programm ing.
<---- Host Command ----> < Ncr Cycles > <----- Card response-----> <Host Cmnd>
CMD S T content CRC E Z Z P P * * * * * * P S T content CRC E S T Content
<---------- Card is programming ---------->
DAT D D D D D D D D D D E Z Z S L * * * * * * * * * * * * * * * * * * * * * * E Z Z Z Z Z Z Z Z
<---- Host Command ----> < Ncr Cycles > <----- Card response-----> <Host Cmnd>
CMD S T content CRC E Z Z P P * * * * * * P S T content CRC E S T Content
--Data block-> CRCStatus1
1) The card CRC status response was interrupted by the host.
-----------------------------Card is programming------>
DAT D D D D D Z Z S Status S L L L L * * * * * * * * * * * * * * * * * * * * * * E Z Z Z Z Z Z Z Z
<---- Host Command ----> < Ncr Cycles > <----- Card response-----> <Host Cmnd>
CMD S T content CRC E Z Z P * * * P S T content CRC E S T Content
<---------- Card is programming ---------->
DAT S L * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * L E Z Z Z Z Z Z Z Z
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Functional Description
the timing of the stop command in different card states.
Figure 30: Stop transm ission during data transfer from the host
The card will treat a data block as successfully received and ready for programming only if the CRC
data of the block was validated and the CRC status token sent back to the host. Figure 31 is an
example of an interrupted (by a host stop command) attempt to transmit the CRC status block. The
sequence is identical to all other stop transmission examples. The end bit of the host command is
followed, on the data line, with one more data bit and start of busy signalling. In that case there are
no Z clocks, for switching the bus direction, because the bus direction is already towards the host.
The received data block, in this case is considered incomplete and will not be programmed.
Figure 31: Stop transm ission during CRC status transfer from the card
All previous examples dealt with the scenario of the host stopping the data transmission during an
active data transfer. The following two diagrams describe a scenario of receiving the stop transmission
between data blocks. In the first example the card is busy programming the last block while in
the second the card is idle. However, there are still unprogrammed data blocks in the input buffers.
These blocks are being programmed as soon as the stop transmission command is received and
the card activates the busy signal.
Figure 32: Stop transm ission received after last data block. Card is busy programm ing.
<---- Host Command ----> < Ncr Cycles > <----- Card response-----> <Host Cmnd>
CMD S T content CRC E Z Z P P * * * * * * P S T content CRC E S T Content
<---------- Card is programming ---------->
DAT D D D D D D D D D D E Z Z S L * * * * * * * * * * * * * * * * * * * * * * E Z Z Z Z Z Z Z Z
<---- Host Command ----> < Ncr Cycles > <----- Card response-----> <Host Cmnd>
CMD S T content CRC E Z Z P P * * * * * * P S T content CRC E S T Content
--Data block-> CRCStatus1
1) The card CRC status response was interrupted by the host.
-----------------------------Card is programming------>
DAT D D D D D Z Z S Status S L L L L * * * * * * * * * * * * * * * * * * * * * * E Z Z Z Z Z Z Z Z
<---- Host Command ----> < Ncr Cycles > <----- Card response-----> <Host Cmnd>
CMD S T content CRC E Z Z P * * * P S T content CRC E S T Content
<---------- Card is programming ---------->
DAT S L * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * L E Z Z Z Z Z Z Z Z
DO NOT COPY (c)2000 (c)2001 by SD Group (MEI,SanDisk,Toshiba)

Date: April 2001

<---- Host Command ---->

< Ncr Cycles >

<----- Card response----->

content

CRC

* * *

content

CRC

Content

<---------- Card is programming ---------->

* * * * * * * * * * * * * * * * * * * * *

CMD
DAT

Figure 33: Stop transmission received after last data block. Card becomes busy.

‧ Erase, Set and Clear Write Protect Timing.
The host must first tag the start (CMD32) and end (CMD33) addresses of the range to be erased.
The erase command (CMD38), once issued, will erase all the selected write blocks. Similarly, set
and clear write protect commands start a programming operation as well. The card will signal “busy”
(by pulling the DAT line low) for the duration of the erase or programming operation. The bus transaction
timings are the same as given for stop tran command in Figure 33.

‧ Reselecting a busy card
When a busy card which is currently in the dis state is reselected it will reinstate its busy signaling
on the data line. The timing diagram for this command / response / busy transaction is the same as
given for stop tran command in Figure 33.

4.12.4 Timing Values
Table 26 defines all timing values.

M in Max Unit
NCR 2 64 clock cycles
NID 5 5 clock cycles
NAC(note 1) 2 -clock cycles
NRC 8 -clock cycles
NCC 8 -clock cycles
NWR 2 -clock cycles

(1) NAC is the sum of TAAC + NSAC (refer to Chapter 5.3)
Table 26: Timing values

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SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01 SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
Card Registers

5 Card Registers

Within the card interface six registers are defined: OCR, CID, CSD, RCA, DSR and SCR. These can
be accessed only by corresponding commands (see Chapter 4.7). The OCR, CID, CSD and SCR
registers carry the card/content specific information, while the RCA and DSR registers are configuration
registers storing actual configuration parameters.

5.1 OCR Register
The 32-bit operation conditions register stores the VDD voltage profile of the card. In addition, this
register includes a status information bit. This status bit is set if the card power up procedure has
been finished. The OCR register shall be implemented by the cards which do not support the full
operating voltage range of the SD Memory Card bus, or if the card power up extends the definition

in the timing diagram (Figure 37).

OCR bit position

VDD voltage window

3.2-3.3
3.3-3.4
3.4-3.5
3.5-3.6
reserved
card power up status bit (busy)1

Table 27: OCR register definition

1)This bit is set to LOW if the card has not finished the power up routine

reserved
1.6-1.7
1.7-1.8
1.8-1.9
1.9-2.0
2.0-2.1
2.1-2.2
2.2-2.3
2.3-2.4
2.4-2.5
2.5-2.6
2.6-2.7
2.7-2.8
2.8-2.9
2.9-3.0
3.0-3.1
3.1-3.2

0-3

24-30

The supported voltage range is coded as shown in Table 27. A voltage range is not supported if the
corresponding bit value is set to LOW. As long as the card is busy, the corresponding bit (31) is set

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Card Registers

to LOW.

5.2 CID Register
The Card IDentification (CID) register is 128 bits wide. It contains the card identification information
used during the card identification phase. Every individual flash card shall have a unique identification
number. The structure of the CID register is defined in the following paragraphs:

Name Field W idth CID-slice
Manufacturer ID MID 8 [127:120]
OEM/Application ID OID 16 [119:104]
Product name PNM 40 [103:64]
Product revision PRV 8 [63:56]
Product serial number PSN 32 [55:24]
reserved -4
[23:20]
Manufacturing date MDT 12 [19:8]
CRC7 checksum CRC 7 [7:1]
not used, always ’1’ -1 [0:0]

Table 28: The CID fields

An 8 bit binary number that identifies the card manufacturer. The MID number is controlled, defined
and allocated to a SD Memory Card manufacturer by the SD Group. This procedure is established
to ensure uniqueness of the CID register.

A 2 ASCII string characters that identifies the card OEM and/or the card contents (when used as a
distribution media either on ROM or FLASH cards). The OID number is controlled, defined and allocated
to a SD Memory Card manufacturer by the SD Group. This procedure is established to
ensure uniqueness of the CID register.

The product name is a string, 5 ASCII characters long.

The product revision is composed of two Binary Coded Decimal (BCD) digits, four bits each, representing
an “n.m” revision number. The “n” is the most significant nibble and “m” is the least signifi-

As an example, the PRV binary value field for product revision “6.2” will be: 0110 0010

‧ M ID
‧ OID
‧ PNM
‧ PRV
cant nibble.

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Card Registers

‧ PSN
The Serial Number is 32 bits of binary number.

‧ MDT
The manufacturing date composed of two hexadecimal digits, one is 8 bit representing the year(y)
and the other is four bits representing the month(m).
The “m” field [11:8] is the month code. 1 = January.
The “y” field [19:12] is the year code. 0 = 2000.
As an example, the binary value of the Date field for production date “April 2001” will be:
00000001 0100.

‧ CRC
CRC7 checksum (7 bits). This is the checksum of the CID contents computed according to Chapter 7.

5.3 CSD Register
The Card-Specific Data register provides information on how to access the card contents. The CSD
defines the data format, error correction type, maximum data access time, whether the DSR register
can be used etc. The programmable part of the register (entries marked by W or E, see below) can be
changed by CMD27. The type of the entries in the table below is coded as follows: R = readable,
W(1) = writable once, W = multiple writable.

Name Field
Co., Ltd.
W idth Cell
Type CSD-slice
CSD structure CSD_STRUCTURE 2 R [127:126]
reserved -6 R [125:120]
data read access-time-1 TAAC 8 R [119:112]
data read access-time-2 in CLK
cycles (NSAC*100)
NSAC 8 R [111:104]
max. data transfer rate TRAN_SPEED 8 R [103:96]
card command classes CCC 12 R [95:84]
max. read data block length READ_BL_LEN 4 R [83:80]
partial blocks for read allowed READ_BL_PARTIAL 1 R [79:79]
write block misalignment WRITE_BLK_MISALIGN 1 R [78:78]
read block misalignment READ_BLK_MISALIGN 1 R [77:77]
DSR implemented DSR_IMP 1 R [76:76]
reserved -2 R [75:74]
device size C_SIZE 12 R [73:62]
max. read current @VDD min VDD_R_CURR_MIN 3 R [61:59]
max. read current @VDD max VDD_R_CURR_MAX 3 R [58:56]
max. write current @VDD min VDD_W_CURR_MIN 3 R [55:53]

Table 29: The CSD Register fields

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SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01 SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
Card Registers

Name Field W idth Cell
Type CSD-slicemax. write current @VDD max VDD_W_CURR_MAX 3 R [52:50]
device size multiplier C_SIZE_MULT 3 R [49:47]
erase single block enable ERASE_BLK_EN 1 R [46:46]
erase sector size SECTOR_SIZE 7 R [45:39]
write protect group size WP_GRP_SIZE 7 R [38:32]
write protect group enable WP_GRP_ENABLE 1 R [31:31]
reserved for MultiMediaCard compatibility 2 R [30:29]
write speed factor R2W_FACTOR 3 R [28:26]
max. write data block length WRITE_BL_LEN 4 R [25:22]
partial blocks for write allowed WRITE_BL_PARTIAL 1 R [21:21]
reserved -5 R [20:16]
File format group FILE_FORMAT_GRP 1 R/W(1) [15:15]
copy flag (OTP) COPY 1 R/W(1) [14:14]
permanent write protection PERM_WRITE_PROTECT 1 R/W(1) [13:13]
temporary write protection TMP_WRITE_PROTECT 1 R/W [12:12]
File format FILE_FORMAT 2 R/W(1) [11:10]
reserved 2 R/W [9:8]
CRC CRC 7 R/W [7:1]
not used, always’1’ -1 -[0:0]

Table 29: The CSD Register fields

The following sections describe the CSD fields and the relevant data types. If not explicitly defined
otherwise, all bit strings are interpreted as binary coded numbers starting with the left bit first.

‧ CSD_STRUCTURE
Version number of the related CSD structure.

CSD_STRUCTURE CSD structure version Valid for SD Memory Card Physical
Specification Version
0 CSD version No. 1.0 Version 1.0
1-3 reserved

Table 30: CSD register structure

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Card Registers

‧ TAAC
Defines the asynchronous part of the data access time.

TAAC bit
position code
2:0 time unit
0=1ns, 1=10ns, 2=100ns, 3=1μs, 4=10μs,
5=100μs, 6=1ms, 7=10ms

6:3
7

time value
0=reserved, 1=1.0, 2=1.2, 3=1.3, 4=1.5,
5=2.0, 6=2.5, 7=3.0, 8=3.5, 9=4.0, A=4.5,
B=5.0, C=5.5, D=6.0, E=7.0, F=8.0

reserved

Table 31: TAAC access time definition

Defines the worst case for the clock dependent factor of the data access time. The unit for NSAC is
100 clock cycles. Therefore, the maximal value for the clock dependent part of the data access time

The total access time NAC as expressed in the Table is the sum of TAAC and NSAC. It has to be
computed by the host for the actual clock rate. The read access time should be interpreted as a typical
delay for the first data bit of a data block or stream.

The following table defines the maximum data transfer rate per one data line - TRAN_SPEED:

TRAN_SPEED bit

B=5.0, C=5.5, D=6.0, E=7.0, F=8.0
reserved

Table 32: Maximum data transfer rate definition

Note that for current SD Memory Cards that field must be always 032h which is equal to 25MHz the
mandatory maximum operating frequency of SD Memory Card.

The SD Memory Card command set is divided into subsets (command classes). The card command
class register CCC defines which command classes are supported by this card. A value of ‘1’ in a

‧ NSAC
code

transfer rate unit
0=100kbit/s, 1=1Mbit/s, 2=10Mbit/s,
3=100Mbit/s, 4... 7=reserved

time value
0=reserved, 1=1.0, 2=1.2, 3=1.3, 4=1.5,
5=2.0, 6=2.5, 7=3.0, 8=3.5, 9=4.0, A=4.5,

is 25.5k clock cycles.

‧ TRAN_SPEED
2:0
6:3
7

‧ CCC
CCC bit means that the corresponding command class is supported. For command class definition
refer to Table 8.

CONFIDENTIAL
65

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SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01 SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
Card Registers

CCC bit Supported card command class
0 class 0
1 class 1
......
11 class 11

Table 33: Supported card command classes

‧ READ_BL_LEN
The maximum read data block length is computed as 2READ_BL_LEN. The maximum block length
might therefore be in the range 512...2048 bytes (see Chapter 4.11 for details). Note that in SD
Memory Card the WRITE_BL_LEN is always equal to READ_BL_LEN

READ_BL_LEN Block length Remark
0-8 reserved
9 29 = 512 Bytes
......
11 211 = 2048 Bytes
12-15 reserved

Table 34: Data block length

AL (always = 1 in SD Memory Card)

Partial Block Read is always allowed in SD Memory Card. It means that smaller blocks can be used
as well. The minimum block size will be one byte.

TE_BLK_MISALIGN
Defines if the data block to be written by one command can be spread over more than one physical
block of the memory device. The size of the memory block is defined in WRITE_BL_LEN.
WRITE_BLK_MISALIGN=0 signals that crossing physical block boundaries is invalid.
WRITE_BLK_MISALIGN=1 signals that crossing physical block boundaries is allowed.

‧ READ_BLK_MISALIGN
Defines if the data block to be read by one command can be spread over more than one physical
block of the memory device. The size of the memory block is defined in READ_BL_LEN.
READ_BLK_MISALIGN=0 signals that crossing physical block boundaries is invalid.
READ_BLK_MISALIGN=1 signals that crossing physical block boundaries is allowed.

‧ READ_BL_PARTI
‧ WRI
‧ DSR_IMP
Defines if the configurable driver stage is integrated on the card. If set, a driver stage register (DSR)

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Card Registers

must be implemented also (see Chapter 5.5).

DSR_IMP DSR type
0 no DSR implemented
1 DSR implemented

Table 35: DSR implementation code table

‧ C_SIZE
This parameter is used to compute the user’s data card capacity (not include the security protected
area). The memory capacity of the card is computed from the entries C_SIZE, C_SIZE_MULT and
READ_BL_LEN as follows:

memory capacity = BLOCKNR * BLOCK_LEN

BLOCKNR = (C_SIZE+1) * MULT
MULT = 2C_SIZE_MULT+2

BLOCK_LEN = 2READ_BL_LENTherefore, the maximal capacity which can be coded is 4096*512*2048 = 4 GBytes. Example: A 32
MByte card with BLOCK_LEN = 512 can be coded by C_SIZE_MULT = 3 and C_SIZE = 2000.

The maximum values for read and write currents at the minimal power supply VDD are coded as fol-

VDD_R_CURR_MIN
VDD_W_CURR_MIN

‧ VDD_R_CURR_MAX, VDD_W_CURR_MAX
The maximum values for read and write currents at the maximal power supply VDD are coded as fol-

VDD_R_CURR_MAX

code for current consumption @ VDD

VDD_W_CURR_MAX

0=1mA; 1=5mA; 2=10mA; 3=25mA; 4=35mA;
5=45mA; 6=80mA; 7=200mA

Table 37: VDD,max current consumption

where

(C_SIZE_MULT < 8)
, (READ_BL_LEN < 12)

N, VDD_W _CURR_MIN

code for current consumption @ VDD

0=0.5mA; 1=1mA; 2=5mA; 3=10mA; 4=25mA;
5=35mA; 6=60mA; 7=100mA

Table 36: VDD,min current consumption

‧ VDD_R_CURR_MI
lows:

2:0
lows:

2:0
‧ C_SIZE_MULT
This parameter is used for coding a factor MULT for computing the total device size (see ‘C_SIZE’).

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Card Registers

The factor MULT is defined as 2C_SIZE_MULT+2 .

C_SIZE_MULT MULT Remark
0 22 = 4
1 23 = 8
2 24 = 16
3 25 = 32
4 26 = 64
5 27 = 128
6 28 = 256
7 29 = 512

Table 38: Multiply factor for the device size

Defines whether erase of one write block (see WRITE_BL_LEN) is allowed (beside the
SECTOR_SIZE given bellow).
If ERASE_BLK_EN = ’0’ erase area is unit of SECTOR_SIZE.
if ERASE_BLK_EN = ’1’ erase area is unit of SECTOR_SIZE or unit of WRITE_BL_LEN.

The size of an erasable sector. The contents of this register is a 7 bit binary coded value, defining
the number of write blocks (see WRITE_BL_LEN). The actual size is computed by increasing this
number by one. A value of zero means 1 write block, 127 means 128 write blocks.

The size of a write protected group. The contents of this register is a 7 bit binary coded value, defining
the number of erase sectors (see SECTOR_SIZE). The actual size is computed by increasing
this number by one. A value of zero means 1 erase sector, 127 means 128 erase sectors.

‧ WP_GRP_ENABLE
A value of ‘0’ means no group write protection possible.

Defines the typical block program time as a multiple of the read access time. The following table

‧ ERASE_BLK_EN
‧ SECTOR_SIZE
‧ WP_GRP_SIZE
‧ R2W_FACTOR
defines the field format.

R2W_FACTOR Multiples of read access time
0 1
1 2 (write half as fast as read)

Table 39: R2W _FACTOR

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Card Registers

R2W_FACTOR Multiples of read access time2 4
3 8
4 16
5 32
6,7 reserved

Table 39: R2W _FACTOR

‧ WR ITE_BL_LEN
The maximum write data block length is computed as 2WRITE_BL_LEN. The maximum block length
might therefore be in the range from 512 up to 2048 bytes. Write Block Length of 512 bytes is

always supported.
Note that in SD Memory Card the WRITE_BL_LEN is always equal to READ_BL_LEN.

Table 40: Data block length

Defines whether partial block sizes can be used in block write commands.

WRITE_BL_PARTIAL=’0’ means that only the WRITE_BL_LEN block size and its partial derivatives,
in resolution of units of 512 bytes, can be used for block oriented data write.
WRITE_BL_PARTIAL=’1’ means that smaller blocks can be used as well. The minimum block size

‧ FILE_FORMAT_GRP
Indicates the selected group of file formats. This field is read-only for ROM. The usage of this field is
shown in Table 41 (see FILE_FORMAT).

Defines if the contents is original (= ‘0’) or has been copied (=’1’). The COPY bit for OTP and MTP
devices, sold to end consumers, is set to ‘1’ which identifies the card contents as a copy. The COPY
bit is an one time programmable bit.

WR ITE_BL_LEN Block length Remark
0-8 reserved
9 29 = 512 Bytes
......
11 211 = 2048 Bytes
12-15 reserved

‧ WR ITE_BL_PARTI
is one byte.

‧ COPY
‧ PERM_WRITE_PROTECT
Permanently protects the whole card content against overwriting or erasing (all write and erase

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Card Registers

commands for this card are permanently disabled). The default value is ‘0’, i.e. not permanently
write protected.

‧ TMP_WRITE_PROTECT
Temporarily protects the whole card content from being overwritten or erased (all write and erase
commands for this card are temporarily disabled). This bit can be set and reset. The default value is
‘0’, i.e. not write protected.

‧ FILE_FORMAT
Indicates the file format on the card. This field is read-only for ROM. The following formats are
defined:

Table 41: File formats

A more detailed description is given in SD Memory Card File System specification.

‧ CRC
The CRC field carries the check sum for the CSD contents. It is computed according to Chapter 7.2.
The checksum has to be recalculated by the host for any CSD modification. The default corresponds
to the initial CSD contents.

The following table lists the correspondence between the CSD entries and the command classes. A
‘+’ entry indicates that the CSD field affects the commands of the related command class.

FILE_
FORMAT_
GRP
FILE_FORMAT Type
0 0 Hard disk-like file system with partition table
0 1 DOS FAT (floppy-like) with boot sector only (no partition table)
0 2 Universal File Format
0 3 Others / Unknown
1 0, 1, 2, 3 Reserved

Command classes
CSD Field 0 2 4 5 6 7 8 9
CSD_STRUCTURE + + + + + + + +
TAAC + + + + + +
NSAC + + + + + +

Table 42: Cross reference of CSD fields vs. command classes

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Card Registers

CSD Field 0 2 4 5 6 7 8 9TRAN_SPEED + +
CCC + + + + + + + +
READ_BL_LEN +
WRITE_BLK_MISALIGN +
READ_BLK_MISALIGN +
DSR_IMP + + + + + + + +
C_SIZE_MANT + + + + + +
C_SIZE_EXP + + + + + +
VDD_R_CURR_MIN +

Command classes

VDD_R_CURR_MAX

+
VDD_W_CURR_MIN

+
VDD_W_CURR_MAX

+
+
+
+
+
+
+
+

+
+

+
SECTOR_SIZE

ERASE_BLK_EN

+
WP_GRP_SIZE

+
WP_GRP_ENABLE

+
R2W_FACTOR

+
WRITE_BL_LEN

+
WRITE_BL_PARTIAL

+
FILE_FORMAT_GRP
+

+
PERM_WRITE_PROTECT

+
TMP_WRITE_PROTECT

+
FILE_FORMAT
+

Table 42: Cross reference of CSD fields vs. command classes

COPY

CRC

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Card Registers

Description Field W idth Cell
Type
SCR
Slice
SCR Structure SCR_STRUCTURE 4 R [63:60]
SD Memory Card - Spec. Version SD_SPEC 4 R [59:56]
data_status_after erases DATA_STAT_AFTER_ERASE 1 R [55:55]
SD Security Support SD_SECURITY 3 R [54:52]
DAT Bus widths supported SD_BUS_WIDTHS 4 R [51:48]
reserved -16 R [47:32]
reserved for manufacturer usage -32 R [31:0]

5.4 RCA Register
The writable 16-bit relative card address register carries the card address that is published by the
card during the card identification. This address is used for the addressed host-card communication
after the card identification procedure. The default value of the RCA register is 0x0000. The value
0x0000 is reserved to set all cards into the Stand-by State with CMD7.

5.5 DSR Register (Optional)
The 16-bit driver stage register is described in detail in Chapter 6.5. It can be optionally used to
improve the bus performance for extended operating conditions (depending on parameters like bus
length, transfer rate or number of cards). The CSD register carries the information about the DSR

Taisol

Electronics

5.6 SCR Register
In addition to the CSD register there is another configuration register that named - SD CARD Configuration
Register (SCR). SCR provides information on SD Memory Card's special features that
were configured into the given card. The size of SCR register is 64 bit. This register shall be set in
the factory by the SD Memory Card manufacturer.

Co., Ltd.

The following table describes the SCR register content.

Table 43: The SCR Fields

‧ SCR_STRUCTURE
Version number of the related SCR structure in the SD Memory Card Physical Layer Specification.

CSD_STRUCTURE CSD structure version Valid for SD Physical Layer
Specification Version
0 SCR version No. 1.0 Version 1.0
1-15 reserved

Table 44: SCR register structure version

‧ SD_SPEC
Describes the SD Memory Card Physical Layer Specification version supported by this card.

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Card Registers

SPEC_VERS Physical Layer Specification Version
Number
0 Version 1.0
1-15 reserved

Table 45: SD Memory Card Physical Layer Specification Version

‧ DATA_STAT_AFTER_ERASE
Defines the data status after erase, whether it is ‘0’ or ‘1’ (the status is card vendor dependent).

‧ SD_SECURITY
Describes the security algorithm supported by the card.

SD_SECURITY Supported algorithm
0 no security
1 security protocol 1.0
2 security protocol 2.0
3 .. 7 reserved

Bit 1

reserved
Bit 2

4 bit (DAT0-3)
Bit 3 [MSB]

reserved

Table 47: SD Memory Card Supported Bus Widths

Since SD Memory Card shall support at least the two bus modes 1bit or 4bit width then any SD
Card shall set at least bits 0 and 2 (SD_BUS_WIDTH="0101").

Table 46: SD Supported security algorithm

Security Protocol 1.0 relates to Security Specification Version 0.96.
Security Protocol 2.0 relates to Security Specification Version 1.0.
Note that it is mandatory for a Writable SD Memory Card (OTP or R/W) to support Security Protocol.
For ROM (Read Only) type of SD Memory Card the security feature is optional.

Describes all the DAT bus widths that are supported by this card.

SD_BUS_WIDTHS

Supported Bus Widths

Bit 0

1 bit (DAT0)

‧ SD_BUS_WIDTHS
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SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Hardware Interface
6 SD Memory Card Hardware Interface
The SD Memory Card has six communication lines and three supply lines:
‧ CMD: Command is a bidirectional signal. The host and card drivers are operating in push pull
mode.
‧ DAT0-3: Data lines are bidirectional signals. Host and card drivers are operating in push pull
mode
‧ CLK: Clock is a host to card signal. CLK operates in push pull mode
‧ VDD: VDD is the power supply line for all cards.
‧ VSS1, VSS2 are two ground lines.
In addition to those lines that are connected to the internal card circuitry there are two contacts of
the Write Protect/Card Detect switch that are part of the socket. Those contacts are not mandatory
but if they are exist they should be connected as given in the following figure.
When DAT3 is used for card detection, RDAT for DAT3 should be unconnected and an another
resistor should be connected to the ground.
Figure 34: Bus circuitry diagram
RDAT and RCMD are pull-up resistors protecting the CMD and the DAT lines against bus floating
when no card is inserted or when all card drivers are in an high-impedance mode.
The host shall pull-up all DAT0-3 lines by RDAT, even if the host uses SD Memory Card as 1 bit-
mode-only in SD mode. Also, the host shall pull-up all "RSV" lines in SPI mode, eventhough they
are not used.
RWP is used for the Write Protect/Card Detection switch.
Refer to Chapter 6.6 for components values and conditions.
6.1 Hot insertion and removal
To guarantee the proper sequence of card pin connection during hot insertion, the use of either a
CMD
CLK
DAT0-3
SD
Memory
Card
Host 1 2 3 4 5 6 7 8
SD Memory
Card
RDAT RCMD
C1 C2 C3
9
RWP
VssWrite Protect
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Hardware Interface
6 SD Memory Card Hardware Interface
The SD Memory Card has six communication lines and three supply lines:
‧ CMD: Command is a bidirectional signal. The host and card drivers are operating in push pull
mode.
‧ DAT0-3: Data lines are bidirectional signals. Host and card drivers are operating in push pull
mode
‧ CLK: Clock is a host to card signal. CLK operates in push pull mode
‧ VDD: VDD is the power supply line for all cards.
‧ VSS1, VSS2 are two ground lines.
In addition to those lines that are connected to the internal card circuitry there are two contacts of
the Write Protect/Card Detect switch that are part of the socket. Those contacts are not mandatory
but if they are exist they should be connected as given in the following figure.
When DAT3 is used for card detection, RDAT for DAT3 should be unconnected and an another
resistor should be connected to the ground.
Figure 34: Bus circuitry diagram
RDAT and RCMD are pull-up resistors protecting the CMD and the DAT lines against bus floating
when no card is inserted or when all card drivers are in an high-impedance mode.
The host shall pull-up all DAT0-3 lines by RDAT, even if the host uses SD Memory Card as 1 bit-
mode-only in SD mode. Also, the host shall pull-up all "RSV" lines in SPI mode, eventhough they
are not used.
RWP is used for the Write Protect/Card Detection switch.
Refer to Chapter 6.6 for components values and conditions.
6.1 Hot insertion and removal
To guarantee the proper sequence of card pin connection during hot insertion, the use of either a
CMD
CLK
DAT0-3
SD
Memory
Card
Host 1 2 3 4 5 6 7 8
SD Memory
Card
RDAT RCMD
C1 C2 C3
9
RWP
VssWrite Protect
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SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Hardware Interface
special hot-insertion capable card connector or an auto-detect loop on the host side (or some similar
mechanism) is mandatory (see Chapter 8).
No card shall be damaged by inserting or removing a card into the SD Memory Card bus even when
the power (VDD) is up. Data transfer operations are protected by CRC codes, therefore any bit
changes induced by card insertion and removal can be detected by the SD Memory Card bus master.
The inserted card must be properly reset also when CLK carries a clock frequency fPP. Each card
shall have power protection to prevent card (and host) damage. Data transfer failures induced by
removal/insertion are detected by the bus master. They must be corrected by the application, which
may repeat the issued command.
6.2 Card Detection (Insertion/Removal)
In order to be able to give feedback indication to the users, SD Memory Card system shall implement
detection of card insertion or removal. One method is by sensing pin 1 of the card, and detecting
the pull-up resistance on it. Detailed description of this and several other card detection options
is given in Application Note “Card Detection Implementations”. In any case since it is not guaranty
that all the MultiMediaCards in the market support the proposed card detection methods in SD
Memory Card then the SD Memory Card host shall not ignore non-detected cards (empty sockets).
If the host gets command from the user to operate a card it shall try to initialize a card in the socket
even if no card insertion was previously reported - just in case that MultiMediaCards that do not support
the card detection method is inside the socket.
6.3 Power protection (Insertion/Removal)
Cards shall be inserted/removed into/from the bus without damage. If one of the supply pins (VDD or
VSS) is not connected properly, then the current is drawn through a data line to supply the card.
Figure 35: Improper power supply
Card
Controller
VDD
Vss
CMD, DAT,
VDD not connected
Vss not connected
CLK

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SD Memory Card Hardware Interface
Every card’s output also shall be able to withstand shortcuts to either supply.
If hot insertion feature is implemented in the host, than the host has to withstand an instant shortcut
between VDD and VSS without damage.
6.4 Power up
The power up of the SD Memory Card bus is handled locally in each SD Memory Card and in the
bus master.
Figure 36: Short cut protection
VDD
Vss
CMD, DAT,CLK
i short
i short
worst case shortcut
Connector

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SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Hardware Interface
‧ After power up (including hot insertion, i.e. inserting a card when the bus is operating) the SD
Memory Card enters the idle state. During this state the SD Memory Card ignores all bus transactions
until ACMD41 is received (ACMD command type shall always precede with CMD55).
‧ ACMD41 is a special synchronization command used to negotiate the operation voltage range
and to poll the cards until they are out of their power-up sequence. Besides the operation voltage
profile of the cards, the response to ACMD41 contains a busy flag, indicating that the card is still
working on its power-up procedure and is not ready for identification. This bit informs the host
that the card is not ready. The host has to wait (and continue to poll the cards, each one on his
turn) until this bit is cleared. The maximum period of power up procedure of single card shall not
exceed 1 second.
‧ Getting individual cards, as well as the whole SD Memory Card system, out of idle state is up to
the responsibility of the bus master. Since the power up time and the supply ramp up time
depend on application parameters such as the maximum number of SD Memory Card s, the bus
length and the power supply unit, the host must ensure that the power is built up to the operating
level (the same level which will be specified in ACMD41) before ACMD41 is transmitted.
‧ After power up the host starts the clock and sends the initializing sequence on the CMD line.
This sequence is a contiguous stream of logical ‘1’s. The sequence length is the maximum of
1msec, 74 clocks or the supply-ramp-up-time; The additional 10 clocks (over the 64 clocks after
what the card should be ready for communication) is provided to eliminate power-up synchronization
problems.
Figure 37: Power-up diagram
Logic working Supply voltage
Supply ramp up time
Bus master supply voltage
ACMD
VDD max
Valid voltage range
for commands
CMD0, 15, 55 and
ACMD41
Valid voltage
range for all
other commands
and
memory access
Power up time
Initialization delay:
Optional repetitions of ACMD41
The maximum of
CMD2
NCC
until no cards are responding
with busy bit set.
NCC NCC
1 msec, 74 clock cycles
and supply ramp up time
Initialization sequence 41
ACMD
41
ACMD
41
VDD min
time
Time out value for initialization process = 1Sec
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Hardware Interface
‧ After power up (including hot insertion, i.e. inserting a card when the bus is operating) the SD
Memory Card enters the idle state. During this state the SD Memory Card ignores all bus transactions
until ACMD41 is received (ACMD command type shall always precede with CMD55).
‧ ACMD41 is a special synchronization command used to negotiate the operation voltage range
and to poll the cards until they are out of their power-up sequence. Besides the operation voltage
profile of the cards, the response to ACMD41 contains a busy flag, indicating that the card is still
working on its power-up procedure and is not ready for identification. This bit informs the host
that the card is not ready. The host has to wait (and continue to poll the cards, each one on his
turn) until this bit is cleared. The maximum period of power up procedure of single card shall not
exceed 1 second.
‧ Getting individual cards, as well as the whole SD Memory Card system, out of idle state is up to
the responsibility of the bus master. Since the power up time and the supply ramp up time
depend on application parameters such as the maximum number of SD Memory Card s, the bus
length and the power supply unit, the host must ensure that the power is built up to the operating
level (the same level which will be specified in ACMD41) before ACMD41 is transmitted.
‧ After power up the host starts the clock and sends the initializing sequence on the CMD line.
This sequence is a contiguous stream of logical ‘1’s. The sequence length is the maximum of
1msec, 74 clocks or the supply-ramp-up-time; The additional 10 clocks (over the 64 clocks after
what the card should be ready for communication) is provided to eliminate power-up synchronization
problems.
Figure 37: Power-up diagram
Logic working Supply voltage
Supply ramp up time
Bus master supply voltage
ACMD
VDD max
Valid voltage range
for commands
CMD0, 15, 55 and
ACMD41
Valid voltage
range for all
other commands
and
memory access
Power up time
Initialization delay:
Optional repetitions of ACMD41
The maximum of
CMD2
NCC
until no cards are responding
with busy bit set.
NCC NCC
1 msec, 74 clock cycles
and supply ramp up time
Initialization sequence 41
ACMD
41
ACMD
41
VDD min
time
Time out value for initialization process = 1Sec
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‧
Every bus master shall have the capability to implement ACMD41 and CMD1. CMD1 will be
used to ask MultiMediaCards to send their Operation Conditions. In any case the ACMD41 or the
CMD1 shall be send separately to each card accessing it through its own CMD line.
6.5 Programm able card output driver (Optional)
The bus capacitance of each line of the SD Memory Card bus is the sum of the bus master capacitance,
the bus capacitance itself and the capacitance of each inserted card. The sum of host and
bus capacitance are fixed for one application, but may vary between different applications.The card
load may vary in one application with each of the inserted cards.

In the following, programmable card output drivers for the push pull mode are described as an
optional method for ensuring the defined maximum clock rate independently of the topology and of
the number of inserted cards.

Both data and command driver stages in the push-pull mode have programmable peak current driving
capabilities and programmable rise and fall times. The driver stage register (DSR) consists of
two 8-bit latches. The contents of the latches is calculated from the required transfer speed of the
interface and the bus load.

The CMD and DAT bus drivers consist of a predriver stage and a complementary driver transistor
(Figure 38). The predriver stage output rise and fall time is set with the DSR1 register and determines
the speed of the driver stage. The complementary driver transistor size is set with the DSR2
register and determines the current driving capabilities of the driver stage and also influences the
peak current consumption of the bus driver. The proper combination of both allows the optimum bus

Table 48 defines the DSR register contents:
6 5 4 3
reserved 5ns
2ns
DSR1 7
tswitch-on max
tswitch-on min
20ns
10ns
2 1
100ns
50ns
0
500ns
200ns
6 5 4 3
reserved
100mA
200mA
5ns
DSR2 7
ipeak min
ipeak max
trise typ
20mA
50mA
20ns
2 1
5mA
10mA
100ns
0
1mA
2mA
500ns
Table 48: DSR register contents

The time in DSR1 specifies the switch-on time of the output driver transistors. At the external interface,
it is measurable as a delay time between the clock and driver stage output signal (e.g. for test-

performance.

ing).

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SD Memory Card Hardware Interface
Figure 38: SD Memory Card bus driver
All data is valid for the specified operating range (voltage, temperature). Any combination of DSR1
and DSR2 bits may be programmed. DSR1 has to be programmed for the required clock frequency,
where
fclock = (2 tswitch-on max)-1 .
The DSR2 register must be programmed with the required driver size. Hints for the proper driver
stage selection are part of future application notes (see Appendix).
DAT0-3 out
CMD line in
CMD line out
Drive CMD pin
Drive DAT0-3 pin
Internal card clock
CLK
DAT0-3
CMD
Driver Stage
Register
pad
pad
pad
DAT0-3 line in
4
4
4
4
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Hardware Interface
Figure 38: SD Memory Card bus driver
All data is valid for the specified operating range (voltage, temperature). Any combination of DSR1
and DSR2 bits may be programmed. DSR1 has to be programmed for the required clock frequency,
where
fclock = (2 tswitch-on max)-1 .
The DSR2 register must be programmed with the required driver size. Hints for the proper driver
stage selection are part of future application notes (see Appendix).
DAT0-3 out
CMD line in
CMD line out
Drive CMD pin
Drive DAT0-3 pin
Internal card clock
CLK
DAT0-3
CMD
Driver Stage
Register
pad
pad
pad
DAT0-3 line in
4
4
4
4
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6.6 Bus operating conditions
‧ General
Table 49: Bus Operating Cond. - General
‧ Power supply voltage
Table 50: Bus Operating Cond. - Power Supply Voltage
The current consumption of any card during the power-up period until the first command occure
must not exceed 15 mA averaged over 1 Second. From first command until ’stby_state’ (the state
that the host may read CSD and verify the operating current consumptions) the maximum current
consumtion may be 100mA averaged over 1 Sec. Note that a card that is delivered before fixing
Physical Spec Ver 1.01, may not meet the above initialization current restrictions.
‧ Bus signal line load
The total capacitance CL the CLK line of the SD Memory Card bus is the sum of the bus master
capacitance CHOST, the bus capacitance CBUS itself and the capacitance CCARD of each card connected
to this line:
CL = CHOST + CBUS + N?CCARD
where N is the number of connected cards. Requiring the sum of the host and bus capacitances not
to exceed 30 pF for up to 10 cards, and 40 pF for up to 30 cards, the following values must not be
Parameter Symbol M in Max. Unit Remark
Peak voltage on all lines -0.3 VDD+0.3 V
All Inputs
Input Leakage Current -10 10 ?A
All Outputs
Output Leakage Current -10 10 ?A
Parameter Symbol M in Max. Unit Remark
Supply voltage VDD 2.0 3.6 V
CMD0, 15, 55,
ACMD41
commands
Supply voltage specified in OCR register
Except CMD0,
15, 55,
ACMD41
commands
Supply voltage differentials (VSS1, VSS2) -0.3 0.3 V
Power up time 250 mS from 0v to
VDD M in.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Hardware Interface
6.6 Bus operating conditions
‧ General
Table 49: Bus Operating Cond. - General
‧ Power supply voltage
Table 50: Bus Operating Cond. - Power Supply Voltage
The current consumption of any card during the power-up period until the first command occure
must not exceed 15 mA averaged over 1 Second. From first command until ’stby_state’ (the state
that the host may read CSD and verify the operating current consumptions) the maximum current
consumtion may be 100mA averaged over 1 Sec. Note that a card that is delivered before fixing
Physical Spec Ver 1.01, may not meet the above initialization current restrictions.
‧ Bus signal line load
The total capacitance CL the CLK line of the SD Memory Card bus is the sum of the bus master
capacitance CHOST, the bus capacitance CBUS itself and the capacitance CCARD of each card connected
to this line:
CL = CHOST + CBUS + N?CCARD
where N is the number of connected cards. Requiring the sum of the host and bus capacitances not
to exceed 30 pF for up to 10 cards, and 40 pF for up to 30 cards, the following values must not be
Parameter Symbol M in Max. Unit Remark
Peak voltage on all lines -0.3 VDD+0.3 V
All Inputs
Input Leakage Current -10 10 ?A
All Outputs
Output Leakage Current -10 10 ?A
Parameter Symbol M in Max. Unit Remark
Supply voltage VDD 2.0 3.6 V
CMD0, 15, 55,
ACMD41
commands
Supply voltage specified in OCR register
Except CMD0,
15, 55,
ACMD41
commands
Supply voltage differentials (VSS1, VSS2) -0.3 0.3 V
Power up time 250 mS from 0v to
VDD M in.
CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Hardware Interface
exceeded:
Table 51: Bus Operating Cond. - Signal Line’s Load
Note that the total capacitance of CMD and DAT lines will be consist of CHOST, CBUS and one
CCARD only since they are connected separately to the SD Memory Card host.
6.7 Bus signal levels
As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply
voltage.
Figure 39: Bus signal levels
To meet the requirements of the JEDEC specification JESD8-1A, the card input and output voltages
Parameter Symbol M in Max. Unit Remark
Pull-up resistance RCMD
RDAT
10 100 k? to prevent bus
floating
Bus signal line capacitance CL 250 pF fPP ? 5 MHz,
21 cards
Bus signal line capacitance CL 100 pF fPP ? 20 MHz,
7 cards
Single card capacitance CCARD 10 pF
Maximum signal line inductance 16 nH fPP ? 20 MHz
Pull-up resistance inside card (pin1) RDAT3 10 90 k? May be used for
card detection
VDD
input
input
undefined
V
t
output
output
high level
low level
high level
low level
VOH
VIH
VIL
VOL
VSS
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Hardware Interface
exceeded:
Table 51: Bus Operating Cond. - Signal Line’s Load
Note that the total capacitance of CMD and DAT lines will be consist of CHOST, CBUS and one
CCARD only since they are connected separately to the SD Memory Card host.
6.7 Bus signal levels
As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply
voltage.
Figure 39: Bus signal levels
To meet the requirements of the JEDEC specification JESD8-1A, the card input and output voltages
Parameter Symbol M in Max. Unit Remark
Pull-up resistance RCMD
RDAT
10 100 k? to prevent bus
floating
Bus signal line capacitance CL 250 pF fPP ? 5 MHz,
21 cards
Bus signal line capacitance CL 100 pF fPP ? 20 MHz,
7 cards
Single card capacitance CCARD 10 pF
Maximum signal line inductance 16 nH fPP ? 20 MHz
Pull-up resistance inside card (pin1) RDAT3 10 90 k? May be used for
card detection
VDD
input
input
undefined
V
t
output
output
high level
low level
high level
low level
VOH
VIH
VIL
VOL
VSS
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CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Hardware Interface
shall be within the following specified ranges for any VDD of the allowed voltage range:
Table 52: Bus Signal Cond. - I/O Signal Voltages
6.8 Bus timing
Figure 40: Tim ing diagram data input/output referenced to clock
Parameter Sym bol Min Max. Unit Conditions
Output HIGH voltage VOH 0.75?VDD V IOH=-100 ?A
@VDD min
Output LOW voltage VOL 0.125?VDD V IOL=100 ?A
@VDD min
Input HIGH voltage VIH 0.625?VDD VDD + 0.3 V
Input LOW voltage VIL VSS-0.3 0.25?VDD V
Parameter Symbol M in Max. Unit Remark
Clock CLK (All values are referred to min (VIH) and max (VIL),
Clock frequency Data Transfer Mode fPP 0 25 MHz CL ? 100 pF
(7 cards)
VIL
VIH
VIL
Clock
Input
Output
fPP
tWL tWH
tIH
tTHL tTLH
tODLY(max)
VOH
VOL
VIH
Shaded areas are not valid
tISU
0.7
0.2
tODLY(min)
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card Hardware Interface
shall be within the following specified ranges for any VDD of the allowed voltage range:
Table 52: Bus Signal Cond. - I/O Signal Voltages
6.8 Bus timing
Figure 40: Tim ing diagram data input/output referenced to clock
Parameter Sym bol Min Max. Unit Conditions
Output HIGH voltage VOH 0.75?VDD V IOH=-100 ?A
@VDD min
Output LOW voltage VOL 0.125?VDD V IOL=100 ?A
@VDD min
Input HIGH voltage VIH 0.625?VDD VDD + 0.3 V
Input LOW voltage VIL VSS-0.3 0.25?VDD V
Parameter Symbol M in Max. Unit Remark
Clock CLK (All values are referred to min (VIH) and max (VIL),
Clock frequency Data Transfer Mode fPP 0 25 MHz CL ? 100 pF
(7 cards)
VIL
VIH
VIL
Clock
Input
Output
fPP
tWL tWH
tIH
tTHL tTLH
tODLY(max)
VOH
VOL
VIH
Shaded areas are not valid
tISU
0.7
0.2
tODLY(min)
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Date: April 2001

Parameter Symbol M in Max. Unit Remark
Clock frequency Identification Mode
(the low freq. is required for MultiMediaCard
compatibility).
fOD
0(1)/
100KHz 400 kHz CL ? 250 pF
(21 cards)
Clock low time tWL 10 ns CL ? 100 pF
(7 cards)
Clock high time tWH 10 ns CL ? 100 pF
(7 cards)
Clock rise time tTLH 10 ns CL ? 100 pF
(7 cards)
Clock fall time tTHL 10 ns CL ? 100 pF
(7 cards)
Clock low time tWL 50 ns CL ? 250 pF
(21 cards)
Clock high time
TaisoltWH 50 ns CL ? 250 pF
(21 cards)
Clock rise time tTLH 50 ns CL ? 250 pF
(21 cards)
Clock fall time tTHL 50 ns CL ? 250 pF
(21 cards)
Inputs CMD, DAT (referenced to CLK)
Input set-up time tISU 5 ns CL ? 25 pF
(1 card)
Input hold time tIH 5 ns CL ? 25 pF
(1 card)
Outputs CMD, DAT (referenced to CLK)
Output Delay time during Data Transfer Mode tODLY 0 14 ns CL ? 25 pF
(1 card)
Output Delay time during Identification Mode tODLY 0 50 ns CL ? 25 pF
(1 card)

(1) 0Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is required (refer to
Chapter 4.4 - Clock Control).
Table 53: Bus Timing - Parameters Values

6.9 SDLV Memory Card - Low Voltage SD Memory Cards
Next generation of SD Memory Cards will support operation at lower supply voltage.

Date: April 2001

Parameter Symbol M in Max. Unit Remark
SDLV Memory Card Supply voltage VDD 1.6 3.6 V
for
Identification
and regular
operation
Supply voltage differentials (VSS1, VSS2) -0.2 0.2 V
Power up time 250 mS from 0v to
VDD M in.

Table 54: SDLV Memory Card - Power Supply Voltage

The SDLV Memory Cards (low voltage cards) will support identification and operation voltage
between 1.6V up to 3.6v. That means that the host may operate between 1.6 and 3.6 volts. Though
it is strongly recommended that the host will be developed in such a way that the initialization will be
done in the range of 2.0-3.6 volt. That will allow to communicate with regular SD Memory Cards at
least for the initialization process and then to put them in inactive state in case that the host would
prefer to work in a lower voltage range of SDLV Memory Card rather than SD Memory Card.

Although not mechanically different, new and old cards will not necessarily be interchangeable in a
given system. The system definition allows an attempt to use old (high voltage) cards with new (low
voltage) hosts. In case that the host supports initialization in the range of 2-3.6v the user will be
informed that this is a wrong type of card.

In order to minimize customer dissatisfaction the SDLV Memory Cards will be labeled in such a way
that the user will be able to distinguish between SDLV Memory Cards and regular SD Memory
Cards (2.0-3.6v operation).

The marking method is to be defined [T.B.D].

Date: April 2001

CONFIDENTIAL

SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01 SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SPI Mode

7 SPI Mode

7.1 Introduction
The SPI mode consists of a secondary communication protocol which is offered by Flash-based SD
Memory Cards. This mode is a subset of the SD Memory Card protocol, designed to communicate
with a SPI channel, commonly found in Motorola’s (and lately a few other vendors’) microcontrollers.
The interface is selected during the first reset command after power up (CMD0) and cannot be
changed once the part is powered on.

The SPI standard defines the physical link only, and not the complete data transfer protocol. The SD
Memory Card SPI implementation uses a subset of the SD Memory Card protocol and command
set. The advantage of the SPI mode is the capability of using an off-the-shelf host, hence reducing
the design-in effort to minimum. The disadvantage is the loss of performance of the SPI mode ver

sus SD mode (e.g. Single data line and hardware CS signal per card).

Bus Protocol

While the SD Memory Card channel is based on command and data bit streams which are initiated
by a start bit and terminated by a stop bit, the SPI channel is byte oriented. Every command or data
block is built of 8-bit bytes and is byte aligned to the CS signal (i.e. the length is a multiple of 8 clock

Similar to the SD Memory Card protocol, the SPI messages consist of command, response and
data-block tokens. All communication between host and cards is controlled by the host (master).

The SD Memory Card wakes up in the SD mode. It will enter SPI mode if the CS signal is asserted
(negative) during the reception of the reset command (CMD0) and the card is in idle_state. If the
card recognizes that the SD mode is required it will not respond to the command and remain in the
SD mode. If SPI mode is required the card will switch to SPI and respond with the SPI mode R1

The only way to return to the SD mode is by entering the power cycle. In SPI mode the SD Memory
Card protocol state machine is not observed. All the SD Memory Card commands supported in SPI

7.2 SPI
The host starts every bus transaction by asserting the CS signal low.
The response behavior in the SPI mode differs from the SD mode in the following three aspects:

‧ The selected card always responds to the command.
‧ An additional (8 bit) response structure is used
‧ When the card encounters a data retrieval problem, it will respond with an error response (which
replaces the expected data block) rather than by a time-out as in the SD mode.
In addition to the command response, every data block sent to the card during write operations will
be responded with a special data response token. A data block may be as big as one card write
block (WRITE_BL_LEN) and as small as a single byte. Partial block read/write operations are
enabled by card options specified in the CSD register.

cycles).

7.2.1 Mode Selection
response.

mode are always available.

During the initialization sequence, if the host gets Illegal Command indication for ACMD41 sent to
the card, it may assume that the card is MultiMediaCard. In that case it should re-start the card as

Date: April 2001

CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SPI Mode
MultiMediaCard using CMD0 and CMD1.
7.2.2 Bus Transfer Protection
Every SD Memory Card token transferred on the bus is protected by CRC bits. In SPI mode, the SD
Memory Card offers a non protected mode which enables systems built with reliable data links to
exclude the hardware or firmware required for implementing the CRC generation and verification
functions.
In the non-protected mode the CRC bits of the command, response and data tokens are still
required in the tokens. However, they are defined as ‘don’t care’ for the transmitter and ignored by
the receiver.
The SPI interface is initialized in the non-protected mode. However, the RESET command (CMD0)
which is used to switch the card to SPI mode, is received by the card while in SD mode and, therefore,
must have a valid CRC field.
Since CMD0 has no arguments, the content of all the fields, including the CRC field, are constants
and need not be calculated in run time. A valid reset command is:
0x40, 0x0, 0x0, 0x0, 0x0, 0x95
The host can turn the CRC option on and off using the CRC_ON_OFF command (CMD59).
7.2.3 Data Read
The SPI mode supports single block read and Multiple Block read operations (CMD17 or CMD18 in
the SD Memory Card protocol). Upon reception of a valid read command the card will respond with
a response token followed by a data token of the length defined in a previous SET_BLOCKLEN
(CMD16) command (refer to Figure 41).
Figure 41: Single Block Read operation
A valid data block is suffixed with a 16 bit CRC generated by the standard CCITT polynomial
x16+x12+x5+1.
The maximum block length is given by READ_BL_LEN, defined in the CSD. If partial blocks are
allowed (i.e. the CSD parameter READ_BL_PARTIAL equals 1), the block length can be any number
between 1 and the maximum block size. Otherwise, the only valid block length for data read is
given by READ_BL_LEN.
The start address can be any byte address in the valid address range of the card. Every block, however,
must be contained in a single physical card sector.
commandDataIn
DataOut
from
host
to card
data from card
to host
from
card
to host
data blockresponse
command
Next
Command
CRC
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SPI Mode
MultiMediaCard using CMD0 and CMD1.
7.2.2 Bus Transfer Protection
Every SD Memory Card token transferred on the bus is protected by CRC bits. In SPI mode, the SD
Memory Card offers a non protected mode which enables systems built with reliable data links to
exclude the hardware or firmware required for implementing the CRC generation and verification
functions.
In the non-protected mode the CRC bits of the command, response and data tokens are still
required in the tokens. However, they are defined as ‘don’t care’ for the transmitter and ignored by
the receiver.
The SPI interface is initialized in the non-protected mode. However, the RESET command (CMD0)
which is used to switch the card to SPI mode, is received by the card while in SD mode and, therefore,
must have a valid CRC field.
Since CMD0 has no arguments, the content of all the fields, including the CRC field, are constants
and need not be calculated in run time. A valid reset command is:
0x40, 0x0, 0x0, 0x0, 0x0, 0x95
The host can turn the CRC option on and off using the CRC_ON_OFF command (CMD59).
7.2.3 Data Read
The SPI mode supports single block read and Multiple Block read operations (CMD17 or CMD18 in
the SD Memory Card protocol). Upon reception of a valid read command the card will respond with
a response token followed by a data token of the length defined in a previous SET_BLOCKLEN
(CMD16) command (refer to Figure 41).
Figure 41: Single Block Read operation
A valid data block is suffixed with a 16 bit CRC generated by the standard CCITT polynomial
x16+x12+x5+1.
The maximum block length is given by READ_BL_LEN, defined in the CSD. If partial blocks are
allowed (i.e. the CSD parameter READ_BL_PARTIAL equals 1), the block length can be any number
between 1 and the maximum block size. Otherwise, the only valid block length for data read is
given by READ_BL_LEN.
The start address can be any byte address in the valid address range of the card. Every block, however,
must be contained in a single physical card sector.
commandDataIn
DataOut
from
host
to card
data from card
to host
from
card
to host
data blockresponse
command
Next
Command
CRC
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CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SPI Mode
In case of a data retrieval error, the card will not transmit any data. Instead, a special data error
token will be sent to the host. Figure 42 shows a data read operation which terminated with an error
token rather than a data block.
Figure 42: Read operation - data error
In case of Multiple block read operation every transferred block has its suffixed of 16 bit CRC.
Stop transmission command (CMD12) will actually stop the data transfer operation (the same as in
SD Memory Card operation mode).
Figure 43: Multiple Block Read operation
7.2.4 Data W rite
In SPI mode the SD Memory Card supports single block and Multiple block write commands. Upon
reception of a valid write command (CMD24 or CMD25 in the SD Memory Card protocol), the card
will respond with a response token and will wait for a data block to be sent from the host. CRC suffix,
block length and start address restrictions are (with the exception of the CSD parameter
WRITE_BL_PARTIAL controlling the partial block write option) identical to the read operation (see
Figure 44).
commandDataIn
DataOut
from
host
to card
data error token
from card to host
from
card
to host
data error response
command
Next
Command
commandDataIn
DataOut
from
host
to card
data from card
to host
from
card
to host
data blockresponse
command
Stop Transmission
Command
CRC data block CRC
from
card
to host
response
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SPI Mode
In case of a data retrieval error, the card will not transmit any data. Instead, a special data error
token will be sent to the host. Figure 42 shows a data read operation which terminated with an error
token rather than a data block.
Figure 42: Read operation - data error
In case of Multiple block read operation every transferred block has its suffixed of 16 bit CRC.
Stop transmission command (CMD12) will actually stop the data transfer operation (the same as in
SD Memory Card operation mode).
Figure 43: Multiple Block Read operation
7.2.4 Data W rite
In SPI mode the SD Memory Card supports single block and Multiple block write commands. Upon
reception of a valid write command (CMD24 or CMD25 in the SD Memory Card protocol), the card
will respond with a response token and will wait for a data block to be sent from the host. CRC suffix,
block length and start address restrictions are (with the exception of the CSD parameter
WRITE_BL_PARTIAL controlling the partial block write option) identical to the read operation (see
Figure 44).
commandDataIn
DataOut
from
host
to card
data error token
from card to host
from
card
to host
data error response
command
Next
Command
commandDataIn
DataOut
from
host
to card
data from card
to host
from
card
to host
data blockresponse
command
Stop Transmission
Command
CRC data block CRC
from
card
to host
response
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CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SPI Mode
Figure 44: Single Block W rite operation
Every data block has a prefix of ’Start Block’ token (one byte).
After a data block has been received, the card will respond with a data-response token. If the data
block has been received without errors, it will be programmed. As long as the card is busy programming,
a continuous stream of busy tokens will be sent to the host (effectively holding the DataOut
line low).
Once the programming operation is completed, the host must check the results of the programming
using the SEND_STATUS command (CMD13). Some errors (e.g. address out of range, write protect
violation etc.) are detected during programming only. The only validation check performed on
the data block and communicated to the host via the data-response token is the CRC and general
Write Error indication.
In Multiple Block write operation the stop transmission will be done by sending ’Stop Tran’ token
instead of ’Start Block’ token at the beginning of the next block. In case of Write Error indication (on
the data response) the host shall use SEND_NUM_WR_BLOCKS (ACMD22) in order to get the
number of well written write blocks. The data tokens description is given in Chapter 7.3.3.
Figure 45: Multiple Block W rite operation
While the card is busy, resetting the CS signal will not terminate the programming process. The card
will release the DataOut line (tri-state) and continue with programming. If the card is reselected
before the programming is finished, the DataOut line will be forced back to low and all commands
will be rejected.
Resetting a card (using CMD0) will terminate any pending or active programming operation. This
may destroy the data formats on the card. It is in the responsibility of the host to prevent it.
data_response
command commandDataIn
DataOut
from
host
to card
new command
from host
data from
host
to card
from
card
to host
data block
busy
Data
response and
busy from
card
response
Start
Block
Token
data_response
command commandDataIn
DataOut
from
host
to card
new command
from hostdata from
host
to card
from
card
to host
data block
busy
Data
response and
busy from
card
response
Start
Block
Token
Stop
Tran
Token
busy
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SPI Mode
Figure 44: Single Block W rite operation
Every data block has a prefix of ’Start Block’ token (one byte).
After a data block has been received, the card will respond with a data-response token. If the data
block has been received without errors, it will be programmed. As long as the card is busy programming,
a continuous stream of busy tokens will be sent to the host (effectively holding the DataOut
line low).
Once the programming operation is completed, the host must check the results of the programming
using the SEND_STATUS command (CMD13). Some errors (e.g. address out of range, write protect
violation etc.) are detected during programming only. The only validation check performed on
the data block and communicated to the host via the data-response token is the CRC and general
Write Error indication.
In Multiple Block write operation the stop transmission will be done by sending ’Stop Tran’ token
instead of ’Start Block’ token at the beginning of the next block. In case of Write Error indication (on
the data response) the host shall use SEND_NUM_WR_BLOCKS (ACMD22) in order to get the
number of well written write blocks. The data tokens description is given in Chapter 7.3.3.
Figure 45: Multiple Block W rite operation
While the card is busy, resetting the CS signal will not terminate the programming process. The card
will release the DataOut line (tri-state) and continue with programming. If the card is reselected
before the programming is finished, the DataOut line will be forced back to low and all commands
will be rejected.
Resetting a card (using CMD0) will terminate any pending or active programming operation. This
may destroy the data formats on the card. It is in the responsibility of the host to prevent it.
data_response
command commandDataIn
DataOut
from
host
to card
new command
from host
data from
host
to card
from
card
to host
data block
busy
Data
response and
busy from
card
response
Start
Block
Token
data_response
command commandDataIn
DataOut
from
host
to card
new command
from hostdata from
host
to card
from
card
to host
data block
busy
Data
response and
busy from
card
response
Start
Block
Token
Stop
Tran
Token
busy
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CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SPI Mode
7.2.5 Erase & W rite Protect Management
The erase and write protect management procedures in the SPI mode are identical to those of the
SD mode. While the card is erasing or changing the write protection bits of the predefined sector list,
it will be in a busy state and hold the DataOut line low. Figure 46 illustrates a ‘no data’ bus transaction
with and without busy signalling.
Figure 46: ‘No data’ operations
7.2.6 Read CID/CSD Registers
Unlike the SD Memory Card protocol (where the register contents is sent as a command response),
reading the contents of the CSD and CID registers in SPI mode is a simple read-block transaction.
The card will respond with a standard response token (see Figure 42) followed by a data block of 16
bytes suffixed with a 16 bit CRC.
The data time out for the CSD command cannot be set to the cards TAAC since this value is stored
in the card’s CSD. Therefore the standard response time-out value (NCR) is used for read latency of
the CSD register.
7.2.7 Reset Sequence
The SD Memory Card requires a defined reset sequence. After power on reset or CMD0 (software
reset) the card enters an idle state. At this state the only valid host commands are ACMD41
(SD_SEND_OP_COND), CMD58 (READ_OCR) and CMD59 (CRC_ON_OFF). For the Thick
(2.1mm) SD Memory Card - CMD1 (SEND_OP_COND) is also valid - that means that in SPI mode
CMD1 and ACMD41 have the same behavior, though the usage of CMD41 is preferable since it
allows easy distinguishing between SD Memory Card and MultiMediaCard. For the Thin (1.4mm )
SD Memory Card CMD1 (SEND_OP_COND) is illegal command during the initialization that is
done after power on. After Power On, once the card accepted valid ACMD41, it will be able to
accept also CMD1 even if used after re-initializing (CMD0) the card. It was defined in such way
in order to be able to distinguish between Thin SD Memory Card and MultiMediaCards (that supports
CMD1 as well).
The host must poll the card (by repeatedly sending CMD1 or ACMD41) until the ‘in-idle-state’ bit in
the card response indicates (by being set to 0) that the card completed its initialization processes
and is ready for the next command.
In SPI mode, as opposed to SD mode, ACMD41 (or CMD1 as well, for 2.1mm-SD Memory Card)
has no operands and does not return the contents of the OCR register. Instead, the host may use
CMD58 (available in SPI mode only) to read the OCR register. Furthermore, it is in the responsibility
command commandDataIn
DataOut
from
host
to card
from
host
to card
from
card
to host
response response
from
card
to host
busy
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SPI Mode
7.2.5 Erase & W rite Protect Management
The erase and write protect management procedures in the SPI mode are identical to those of the
SD mode. While the card is erasing or changing the write protection bits of the predefined sector list,
it will be in a busy state and hold the DataOut line low. Figure 46 illustrates a ‘no data’ bus transaction
with and without busy signalling.
Figure 46: ‘No data’ operations
7.2.6 Read CID/CSD Registers
Unlike the SD Memory Card protocol (where the register contents is sent as a command response),
reading the contents of the CSD and CID registers in SPI mode is a simple read-block transaction.
The card will respond with a standard response token (see Figure 42) followed by a data block of 16
bytes suffixed with a 16 bit CRC.
The data time out for the CSD command cannot be set to the cards TAAC since this value is stored
in the card’s CSD. Therefore the standard response time-out value (NCR) is used for read latency of
the CSD register.
7.2.7 Reset Sequence
The SD Memory Card requires a defined reset sequence. After power on reset or CMD0 (software
reset) the card enters an idle state. At this state the only valid host commands are ACMD41
(SD_SEND_OP_COND), CMD58 (READ_OCR) and CMD59 (CRC_ON_OFF). For the Thick
(2.1mm) SD Memory Card - CMD1 (SEND_OP_COND) is also valid - that means that in SPI mode
CMD1 and ACMD41 have the same behavior, though the usage of CMD41 is preferable since it
allows easy distinguishing between SD Memory Card and MultiMediaCard. For the Thin (1.4mm )
SD Memory Card CMD1 (SEND_OP_COND) is illegal command during the initialization that is
done after power on. After Power On, once the card accepted valid ACMD41, it will be able to
accept also CMD1 even if used after re-initializing (CMD0) the card. It was defined in such way
in order to be able to distinguish between Thin SD Memory Card and MultiMediaCards (that supports
CMD1 as well).
The host must poll the card (by repeatedly sending CMD1 or ACMD41) until the ‘in-idle-state’ bit in
the card response indicates (by being set to 0) that the card completed its initialization processes
and is ready for the next command.
In SPI mode, as opposed to SD mode, ACMD41 (or CMD1 as well, for 2.1mm-SD Memory Card)
has no operands and does not return the contents of the OCR register. Instead, the host may use
CMD58 (available in SPI mode only) to read the OCR register. Furthermore, it is in the responsibility
command commandDataIn
DataOut
from
host
to card
from
host
to card
from
card
to host
response response
from
card
to host
busy
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SPI Mode

of the host to refrain from accessing cards that do not support its voltage range.
The usage of CMD58 is not restricted to the initializing phase only, but can be issued at any time.

7.2.8 Error Conditions
Unlike the SD Memory Card protocol, in the SPI mode the card will always respond to a command.
The response indicates acceptance or rejection of the command. A command may be rejected in
any one of the following cases:

-It is sent while the card is in read operation (except CMD12 which is legal).
-It is sent wile the card is in Busy.
- Card is Locked and it is other than Class 0 or 7 commands.
- It is not supported (illegal opcode).
-It contains an illegal operand.
-It was out of sequence during an erase sequence.
Note that in case the host sends command while the card sends data in read operation then the
7.2.12 Copyright Protection commands
All the special Copyright Protection ACMDs and security functionality is the same as for SD mode.

Mode Transaction Packets
Command Tokens

- CRC check failed.
response with an illegal command indication may disturb the data transfer.

Memory Array Partitioning

7.2.10 Card Lock/unlock
Usage of card lock and unlock commands in SPI mode is identical to SD mode. In both cases the
command is responded with a R1b response type. After the busy signal clears, the host should
obtain the result of the operation by issuing a GET_STATUS command. Refer to Chapter 4.3.6 for

7.2.11 Application Specific commands
Identical to SD mode with the exception of the APP_CMD status bit (refer to Chapter 4.10.1) which

7.2.9

Same as for SD mode.

details.

is not available in SPI.

7.3 SPI
7.3.1

‧ Command Format
All the SD Memory Card commands are 6 bytes long. The command transmission always starts

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SPI Mode

with the left bit of the bitstring corresponding to the command codeword. All commands are protected
by a CRC (see Chapter 7.2). The commands and arguments are listed in Table 57.

Bit position 47 46 [45:40] [39:8] [7:1] 0
W idth (bits) 1 1 6 32 7 1
Value ‘0’ ‘1’ x x x ‘1’
Description start bit transmission
bit
command index argument CRC7 end bit

Table 55: Command Format

‧ Command Classes
As in SD mode, the SPI commands are divided into several classes (See Table 56). Each class
supports a set of card functions. A SD Memory Card will support the same set of optional command
classes in both communication modes (there is only one command class table in the CSD register).
The available command classes, and the supported command for a specific class, however, are different
in the SD Memory Card and the SPI communication mode.

Note that except the classes that are not supported in SPI mode (class 1, 3 and 9), the mandatory
required classes for the SD mode are the same for the SPI mode.

Card CMD
Class (CCC) Class Description
Supported commands
0 1 9 10 12 13 16 17 18 24 25 27 28 29 30 32 33 38 42 55 56 58 59
class 0 Basic + + + + + + + +
class 1 Not supported in SPI
class 2 Block read + + +
class 3 Not supported in SPI
class 4 Block write + + +
class 5 Erase + + +
class 6 Write-protection (Optional) + + +
class 7 Lock Card (Optional) +
class 8 Application specific + +
class 9 Not supported in SPI
class 10-11 Reserved

Table 56: Command classes in SPI mode

‧ Detailed Comm and Description
The following table provides a detailed description of the SPI bus commands. The responses are
defined in Chapter 7.3.2. The Table 57 lists all SD Memory Card commands. A “yes” in the SPI
mode colon indicates that the command is supported in SPI mode. With these restrictions, the command
class description in the CSD is still valid. If a command does not require an argument, the
value of this field should be set to zero. The reserved commands are reserved in SD mode as well.

The binary code of a command is defined by the mnemonic symbol. As an example, the content of

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SPI Mode

the command index field is (binary) ‘000000’ for CMD0 and ‘100111’ for CMD39.

CMD
INDEX
SPI
Mode Argument Resp Abbreviation Command Description
CMD0 Yes None R1 GO_IDLE_STATE resets the SD Memory Card
CMD1 Yes7 None R1 SEND_OP_
COND
Activates the card’s initialization process
(In Thin- 1.4mm SD Memory
Card it is valid only if used after re-initializing
a card - see note at Chapter
7.2.7)
CMD2 No
CMD3 No
CMD4 No
CMD5 reserved
CMD6 reserved
CMD7 No
CMD8 reserved
CMD9 Yes None R1 SEND_CSD asks the selected card to send its
card-specific data (CSD)
CMD10 Yes None R1 SEND_CID asks the selected card to send its
card identification (CID)
CMD11 No
CMD12 Yes Non R1b STOP_
TRANSMISSION
forces the card to stop transmission
in Multiple Block Read Operation
CMD13 Yes None R2 SEND_STATUS asks the selected card to send its status
register.
CMD14 reserved
CMD15 No
CMD16 Yes [31:0] block
length
R1 SET_BLOCKLENTaisolElectronicsCo., Ltd.selects a block length (in bytes) for all
following block commands (read and
write).1
CMD17 Yes [31:0] data
address
R1 READ_SINGLE_
BLOCK
reads a block of the size selected by
the SET_BLOCKLEN command.2
CMD18 Yes [31:0] data
address
R1 READ_MULTIPL
E_BLOCK
continuously transfers data blocks
from card to host until interrupted by
a STOP_TRANSMISSION command.
CMD19 reserved
CMD20 No
CMD21
...
CMD23
reserved
CMD24 Yes [31:0] data
address
R1 WRITE_BLOCK writes a block of the size selected by
the SET_BLOCKLEN command. 3

Table 57: Commands and arguments

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SPI Mode

CMD
INDEX
SPI
Mode Argument Resp Abbreviation Command DescriptionCMD25 Yes [31:0] data
address
R1 WRITE_MULTIPL
E_BLOCK
continuously writes blocks of data
until ’Stop Tran’ token is sent (instead
’Start Block’).
CMD26 No
CMD27 Yes None R1 PROGRAM_CSD programming of the programmable
bits of the CSD.
CMD28 Yes [31:0] data
address
R1b4 SET_WRITE_
PROT
if the card has write protection features,
this command sets the write
protection bit of the addressed group.
The properties of write protection are
coded in the card specific data
(WP_GRP_SIZE).
CMD29 Yes [31:0] data
address
R1b CLR_WRITE_
PROT
if the card has write protection features,
this command clears the write
protection bit of the addressed group.
CMD30 Yes [31:0] write
protect data
address
R1 SEND_WRITE_
PROTTaisolElectronicsCo., Ltd.
if the card has write protection features,
this command asks the card to
send the status of the write protection
bits. 5
CMD31 reserved
CMD32 Yes [31:0] data
address
R1 ERASE_WR_BLK
_START_ADDR
sets the address of the first write
block to be erased.
CMD33 Yes [31:0] data
address
R1 ERASE_WR_BLK
_END_ADDR
sets the address of the last write
block of the continuous range to be
erased.
CMD34
...
CMD37
reserved
CMD38 Yes [31:0] stuff bits R1b ERASE erases all previously selected write
blocks
CMD39 No
CMD40 No
CMD41 reserved
CMD42 Yes [31:0] stuff
bits.
R1 LOCK_UNLOCK Used to Set/Reset the Password or
lock/unlock the card. A transferred
data block includes all the command
details - refer to Chapter 4.3.6. The
size of the Data Block is defined with
SET_BLOCK_LEN command.
CMD43
...
CMD54
reserved

Table 57: Commands and arguments

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SPI Mode

CMD
INDEX
SPI
Mode Argument Resp Abbreviation Command DescriptionCMD55 Yes [31:0] stuff bits R1 APP_CMD Defines to the card that the next command
is an application specific command
rather than a standard
command
CMD56 Yes [31:1] stuff
bits.
[0]: RD/WR_6
R1 GEN_CMD Used either to transfer a Data Block
to the card or to get a Data Block
from the card for general purpose /
application specific commands. The
size of the Data Block shall be
defined with SET_BLOCK_LEN command.
CMD57 Reserved
CMD58 Yes None R3 READ_OCR Reads the OCR register of a card.
CMD59 Yes [31:1] stuff bits
[0:0] CRC
option
R1 CRC_ON_OFF Turns the CRC option on or off. A ‘1’
in the CRC option bit will turn the
option on, a ‘0’ will turn it off
CMD60
-63
Reserved For Manufacturer

Table 57: Commands and arguments

1)The default block length is as specified in the CSD.
2)The data transferred must not cross a physical block boundary unless READ_BLK_MISALIGN is set in the
CSD.
3)The data transferred must not cross a physical block boundary unless WRITE_BLK_MISALIGN is set in
the CSD.
4)R1b: R1 response with an optional trailing busy signal.
5) 32 write protection bits (representing 32 write protect groups starting at the specified address) followed by
16 CRC bits are transferred in a payload format via the data line. The last (least significant) bit of the protection
bits corresponds to the first addressed group. If the addresses of the last groups are outside the valid
range, then the corresponding write protection bits shall be set to zero.

6) RD/WR_: “1” the Host shall get a block of data from the card.
“0” the host sends block of data to the card.

7) CMD1 is valid command for the Thin (1.4mm) SD Memory Card only if used after re-initializing a card (not
after power on reset).

The following table describes all the application specific commands supported/reserved by
the SD Memory Card. All the following commands shall be preceded with APP_CMD
(CMD55).

CMD
INDEX
SPI
Mode Argument Resp Abbreviation Command Description
ACMD6 No
ACMD13 yes [31:0] stuff bits R2 SD_STATUS Send the SD Memory Card status.
The status fields are given in Table
24
ACMD17 reserved

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SPI Mode

CMD
INDEX
SPI
Mode Argument Resp Abbreviation Command Description
ACMD18 yes --
-
Reserved
for SD security
applications1
ACMD19
to
ACMD21
reserved
ACMD22 yes [31:0] stuff bits R1 SEND_NUM_WR_
BLOCKS
Send the numbers of the well written
(without errors) blocks. Responds
with 32bit+CRC data block.
ACMD23 yes [31:23] stuff
bits
[22:0]Number
of blocks
R1 SET_WR_BLK_
ERASE_COUNT
Set the number of write blocks to be
pre-erased before writing (to be used
for faster Multiple Block WR command).
“1”=default (one wr block)(2).
ACMD24 reserved
ACMD25 yes --
-
Reserved
for SD security
applications1
ACMD26 yes --
-
Reserved
for SD security
applications1
ACMD38 yes --
-
Reserved
for SD security
applications1
ACMD39
to
ACMD40
reserved
ACMD41 yes None R1 SEND_OP_
COND
Activates the card’s initialization process.
ACMD42 yes [31:1] stuff bits
[0]set_cd
R1 SET_CLR_CARD_
DETECTTaisolConnect[1]/Disconnect[0] the
50KOhm pull-up resistor on CD/DAT3
(pin 1) of the card. The pull-up may
be used for card detection.
ACMD43
...
ACMD49
yes --
-
Reserved
for SD security
applications1
ACMD51 yes [31:0] staff bits R1 SEND_SCR Reads the SD Configuration Register
(SCR).

(1) Refer to “SD Memory Card Security Specification” for detailed explanation about the SD Security Features
(2) Command STOP_TRAN (CMD12) shall be used to stop the transmission in Write Multiple Block whether the pre-erase (ACMD23) feature is used or not.
Table 58: Application Specific Commands used/reserved by SD Memory Card - SPI Mode

7.3.2 Responses
There are several types of response tokens. As in the SD mode, all are transmitted MSB first:

‧ Format R1
This response token is sent by the card after every command with the exception of SEND_STATUS
commands. It is one byte long, and the MSB is always set to zero. The other bits are error indica

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Co., Ltd.
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96 CONFIDENTIAL
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SPI Mode
tions, an error being signaled by a ‘1’. The structure of the R1 format is given in Figure 47. The
meaning of the flags is defined as following:
‧ In idle state: The card is in idle state and running the initializing process.
‧ Erase reset: An erase sequence was cleared before executing because an out of erase
sequence command was received.
‧ Illegal command: An illegal command code was detected.
‧ Communication CRC error: The CRC check of the last command failed.
‧ Erase sequence error: An error in the sequence of erase commands occurred.
‧ Address error:A misaligned address, which did not match the block length, was used in the
command.
‧ Param eter error: The command’s argument (e.g. address, block length) was out of the allowed
range for this card.
Figure 47: R1 Response Format
‧ Format R1b
This response token is identical to the R1 format with the optional addition of the busy signal. The
busy signal token can be any number of bytes. A zero value indicates card is busy. A non-zero
value indicates the card is ready for the next command.
‧ Format R2
This response token is two bytes long and sent as a response to the SEND_STATUS command.
The format is given in Figure 48.
07
in idle state
erase reset
illegal command
com crc error
erase sequence error
address error
parameter error
0

SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SPI ModeTaisolElectronicsCo., Ltd.
Figure 48: R2 response format
The first byte is identical to the response R1. The content of the second byte is described in the following:
‧ Erase param: An invalid selection, sectors or groups, for erase.
‧ W rite protect violation: The command tried to write a write protected block.
‧ Card ECC failed: Card internal ECC was applied but failed to correct the data.
‧ CC error: Internal card controller error
‧ Error: A general or an unknown error occurred during the operation.
‧ W rite protect erase skip | lock/unlock comm and failed: This status bit has two functions overloaded.
It is set when the host attempts to erase a write protected sector or makes a sequence or
password error during card lock/unlock operation.
‧ Card is locked: Set when the card is locked by the user. Reset when it is unlocked.
‧ Format R3
This response token is sent by the card when a READ_OCR command is received. The response
length is 5 bytes (see Figure 49). The structure of the first (MSB) byte is identical to response type
R1. The other four bytes contain the OCR register.
07
Card is locked
wp erase skip | lock/unlock cmd failed
error
CC error
card ecc failed
wp violation
erase param
0
7 0
in idle state
erase reset
illegal command
com crc error
erase sequence error
address error
parameter error
out of range | csd overwrite
1. Byte 2. Byte

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SPI Mode

39 3231 0

0
R1 OCR
Figure 49: R3 Response Format
‧ Data Response

x x x 0
Every data block written to the card will be acknowledged by a data response token. It is one byte
long and has the following format:
7 6 0
Status 1
The meaning of the status bits is defined as follows:
110’ - Data Rejected due to a Write Error
In case of any error (CRC or Write Error) during Write Multiple Block operation, the host shall
stop the data transmission using CMD12. In case of Write Error (response ’110’) the host may send
CMD13 (SEND_STATUS) in order to get the cause of the write problem. ACMD22 can be used to
find the number of well written write blocks.
Read and write commands have data transfers associated with them. Data is being transmitted or
received via data tokens. All data bytes are transmitted MSB first.
Data tokens are 4 to 515 bytes long and have the following format:
For Single Block Read, Single Block Write and Multiple Block Read:
‧ Bytes 2-513 (depends on the data block length): User data
‧ Last two bytes: 16 bit CRC.

70
1

‘010’ - Data accepted.
‘101’ - Data rejected due to a CRC error.

’

7.3.3 Data Tokens
‧ First byte: Start Block
For Multiple Block Write operation:

‧ First byte of each block:
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SPI Mode

If data is to be transferred then - Start Block

7
1 1 1 1 1 1 0
0
0
If Stop transmission is requested - Stop Tran7
1 1 1 1 1 1 0
0
1

Note that this format is used only for Multiple Block Write. In case of Multiple Block Read the stop
transmission is done using STOP_TRAN Command (CMD12).

7.3.4 Data Error Token
If a read operation fails and the card cannot provide the required data, it will send a data error token

7 0
0 0 0 0
Error
CC Error
Card ECC Failed
out of range

ple response types - e.g Card ECC failed)

As in the SD mode, error bits are cleared when read by the host, regardless of the response format.
State indicators are either cleared by reading or in accordance with the card state.
The following table summarizes the set and clear conditions for the various status bits:

instead. This token is one byte long and has the following format:

Figure 50: Data Error Token

The 4 least significant bits (LSB) are the same error bits as in the response format R2.

Clearing Status Bits

As described in the previous paragraphs, in SPI mode, status bits are reported to the host in three
different formats: response R1, response R2 and data error token (the same bits may exist in multi

7.3.5

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SPI Mode

Identifier
Include
d in
resp
Type1 Value Description
Clear
Cond
ition2
Out of range R2
DataErr
E R X ’0’= no error
’1’= error
The command argument was out
of the allowed range for this card.
C
Address error R1 R2 E R X ’0’= no error
’1’= error
A misaligned address which did
not match the block length was
used in the command.
C
Erase
sequence error
R1 R2 E R ’0’= no error
’1’= error
An error in the sequence of erase
commands occurred.
C
Erase param R2 E X ’0’= no error
’1’= error
An error in the parameters of the
erase command sequence
C
Parameter
error
R1 R2 E R X ’0’= no error
’1’= error
An error in the parameters of the
command
C
WP violation R2 E R X ’0’= not protected
’1’= protected
Attempt to program a write protected
block.
C
Com CRC
error
R1 R2 E R ’0’= no error
’1’= error
The CRC check of the previous
command failed.
C
Illegal command
R1 R2 E R ’0’= no error
’1’= error
Command not legal for the card
state
C
Card ECC
failed
R2
DataEr
E X ’0’= success
’1’= failure
Card internal ECC was applied but
failed to correct the data.
C
CC error R2
dataEr
E R X ’0’= no error
’1’= error
Internal card controller error C
Error R2
dataEr
E R X ’0’= no error
’1’= error
A general or an unknown error
occurred during the operation.
C
CID/
CSD_OVERW
RITE
R2 E R X ’0’= no error
’1’= errorTaisolElectronicsCo., Ltd.can be either one of the following
errors:
- The CID register has been
already written and can not be
overwritten
- The read only section of the
CSD does not match the card
content.
- An attempt to reverse the copy
(set as original) or permanent
WP (unprotected) bits was
made.
C
WP erase skip R2 S X ’0’= not protected
’1’= protected
Only partial address space was
erased due to existing write protected
blocks.
C
Lock/Unlock
cmd failed
R2 X ’0’= no error
’1’= error
Sequence or password error during
card lock/unlock operation
C

Table 59: SPI mode status bits

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SPI Mode

Identifier
Include
d in
resp
Type1 Value Description
Clear
Cond
ition2Card is locked R2 S X ‘0’ = card is not
locked
‘1’ = card is
locked
Card is locked by a user password
and
A
Erase reset R1 R2 S R ’0’= cleared
’1’= set
An erase sequence was cleared
before executing because an out
of erase sequence command was
received
C
In Idle state R1 R2 S R 0 = Card is ready
1 = Card is in idle
state
The card enters the idle state after
power up or reset command. It will
exit this state and become ready
upon completion of its initialization
procedures.
A

Table 59: SPI mode status bits

R: Detected and set for the actual command response.
X: Detected and set during command execution. The host must poll the card by issuing the status
command in order to read these bits.
A: According to the card current state.
In SPI mode only the OCR, CSD and CID registers are accessible. Their format is identical to the
format in the SD mode. However, a few fields are irrelevant in SPI mode.

ng Diagrams

All timing diagrams use the following schematics and abbreviations:

1) Type:

E: Error bit.
S: State bit.
2) Clear Condition:

C: Clear by read
7.4 Card Registers
7.5 SPI Bus Timi
H Signal is high (logical ‘1’
L Signal is low (logical ‘0’)
X Don’t care
Z High impedance state (-> = 1)
* Repeater
Busy Busy Token
Command Command token
Response Response token
Data block Data token

101

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SPI Mode

All timing values are defined in Table 60. The host must keep the clock running for at least NCR
clock cycles after receiving the card response. This restriction applies to both command and data
response tokens.

7.5.1 Command / Response
‧ Host Command to Card Response - Card is ready
The following timing diagram describes the basic command response (no data) SPI transaction.

* * * * * * * * * * * * * * * * * * * *

H
<- NCS ->

<- NEC ->

6 Bytes Command

* * * * * * * * *

X
<- NCR ->

DataIN

* * * * * * * * *

1 or 2 Bytes Response

DataOut

Figure 51: Basic command response

‧ Host Command to Card Response - card is busy
The following timing diagram describes the command response transaction for commands when the
card responses which the R1b response type (e.g. SET_WRITE_PROT and ERASE). When the
card is signaling busy, the host may deselect it (by raising the CS) at any time. The card will release
the DataOut line one clock after the CS going high. To check if the card is still busy it needs to be
reselected by asserting (set to low) the CS signal. The card will resume busy signal (pulling DataOut
low) one clock after the falling edge of CS.

* * * * * * * * * * * * * * * * * * * *

H
<- NCS ->

<- NEC -> <- NDS ->

<- NEC ->

DataIN

6 Bytes Command

X
<- NCR ->

DataOut

* * * * * * * * *

Card Resp

Busy

Figure 52: Command response with busy indication (R1b)

‧ Card Response to Host Command
L

* * * * * * * * * * * * * * * * * * * *

* * * * * * * * *

6 Bytes Command

X
<- NRC ->

DataIN

1 or 2 Bytes Response

* * * * * * * * * *

DataOut

Figure 53: Timing between card response to new host command

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SPI Mode

7.5.2 Data read
‧
The following timing diagram describes all single block read operations with the exception of
SEND_CSD and SEND_CID commands.
CS
DataIN
DataOut

H L L L * * * * * * * * * * * * * * * * * * * * L L L H H H H
<- NCS -> <- NEC ->
X H H H H Read Command H H H H H * * * * * * * * * * * * * * * H H H X X X X
<- NCR -> <- NAC ->
Z Z H H H H * * * * * * * * H H H H Card Response H H H H Data Block H H H H Z Z Z

Figure 54: Read Single Block operations - bus tim ing

The following table describes Stop transmission operation in case of Multiple Block Read.

<2clk>

Figure 55: Stop Transm ission in Read Multiple Block

‧ Reading the CSD or CID register
The following timing diagram describes the SEND_CSD and SEND_CID command bus transactions.
The timeout values for the response and the data block are Ncr and Ncx respectively (Since
the Nac is still unknown).

CS
DataIN
DataOut

L L L L * * * * * * * * * * * * * * * * * * * *
<- NCS ->
X H H H H Stop Tran command H H H H H * * * * * * * * * * *
<- NCR ->
Data Transfer to host H H Card Response H

CS
DataIN
DataOut

H L L L * * * * * * * * * * * * * * * * * * * * L L L H H H H
<- NCS -> <- NEC ->
X H H H H Read Command H H H H H * * * * * * * * * * * * * * * H H H X X X X
<- NCR -> <- NCX ->
Z Z H H H H * * * * * * * * H H H H Card Response H H H H Data Block H H H H Z Z Z

Figure 56: Read CSD / CID - bus timing

7.5.3 Data write
The host may deselect a card (by raising the CS) at any time during the card busy period (refer to
the given timing diagram). The card will release the DataOut line one clock after the CS going high.
To check if the card is still busy it needs to be reselected by asserting (set to low) the CS signal.

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SPI Mode

The card will resume busy signal (pulling DataOut low) one clock after the falling edge of CS.

CS
DataIN
DataOut

H L * * * * * * * * * * * * * * * * * * * * L L L L L L L L H H H L L L L
< NCS-> <-NWR-> <- NEC -><- NDS ->
X H H H Write Command H H H H H H H Data Block H H H H H H X X X H H H H
<-NCR->
Z Z H H H * * * * * * * * H H H Card
Response H H H H H H H Data
Resp Busy L Z Z Z Busy H

Figure 57: W rite operation - bus tim ing

The following figure describes stop transmission operation in Multiple Block Write transfer.

(1) The Busy may appear within NBR clocks after Stop Tran Token. If there is no Busy
the host may continue to the next command.
Figure 58: Stop Transmission in Write Multiple Block

7.5.4 Timing Values
CS
Data In

L L L L L L L L L L L L L L L L L L L L L L H H H L L L L
<NWR -> <1byte-> <NBR -> <NEC -> <- NDS ->
Data Block H H H H H H H H H stop tran
token H H H X X X H H H H

H H H H Data
Resp Busy H H H H H H H H H Busy(1)
L Z Z Z Busy(1) H
Data Out

M in Max Unit
NCS 0 -8 clock cycles
NCR 1 8 8 clock cycles
NRC 1 -8 clock cycles
NAC 1 spec. in the CSD 8 clock cycles
NWR 1 -8 clock cycles
NEC 0 -8 clock cycles
NDS 0 -8 clock cycles
NBR 0 1 8 clock cycles
Ncx 0 8 8 clock cycles

Table 60: Timing values

7.6 SPI Electrical Interface
Identical to SD mode with the exception of the programmable card output drivers option which is not
supported in SPI mode.

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SPI Mode

7.7 SPI Bus Operating Conditions
Identical to SD mode

7.8 Bus Timing
Identical to SD mode. The timing of the CS signal is the same as any other card input.

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SD Memory Card mechanical specification

This chapter describes the mechanical and electromechanical features of the SD Memory Card,
and furthermore the minimal recommendations to the SD Memory Card connector. All technical
drafts follow DIN ISO standard.

The functions of the card package are:

-protecting the chip
-easy handling for the end user
-reliable electrical interconnection
-appealing appearance
-reliable write protect/card detection capability
-bearing textual information and image
The functions of the connector are:

-attaching and fixing the card
-electrical interconnecting the card to the system board
-write protect/card detect indication
- optional: switch on/off power supply
-protection against card inverse insertion
Every card package shall have the characteristics described in the following sections.

External signal contacts (ESC)

1.2 mm
2.5mm
1.7mm x 4.0mm
30 m? (worst case: 100 m? )
< 0.1 ?s
Table 61: SD Memory Card Package - External Signal Contacts

8.1 Card package
8.1.1

Number of ESC

distance from front edge

ESC grid

contact dimensions

electrical resistance

micro interrupts

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8.1.2 Design and format
Dimensions SD Memory
Card package
24mm x 32mm; (min. 23.9mm x 31.9mm; max.24.1mm x 32.1mm)
other dimensions Figure 59
testing according to MIL STD 883, Meth 2016
thickness ’Inter Connect Area’: 2.1mm +/- 0.15mm or 1.4mm+/-0.15mm for Thin SD Card.
’Substrate Area’: Max 2.25mm or Max 1.55 for Thin SD Card - see Figure 61.
label or printable area In ’Substrate Area’ only - see Figure 61.
surface plain (except contact area)
edges smooth edges, see Figure 60, Figure 61
inverse insertion protection on left corner (top view) see Figure 63
position of ESC contacts along middle of shorter edge

Table 62: SD Memory Card Package - Dimensions

8.1.3 Reliability and durability
temperature operation: -25°C / 85°C (Target spec)
storage: -40°C (168h) / 85°C (500h)
junction temperature: max. 95°C
moisture and corrosion operation: 25°C / 95% rel. humidity
storage: 40°C / 93% rel. hum./500h
salt water spray:
3% NaCl/35C; 24h acc. MIL STD Method 1009Taisoldurability 10.000 mating cycles; Test procedure: tbd.
bending (note 1) 10N
torque (note 1) 0.15N.m or +/-2.5 deg .
drop test 1.5m free fall
UV light exposure UV: 254nm, 15Ws/cm2 according to ISO 7816-1
visual inspection
shape and form (note 1)
no warpage; no mold skin; complete form; no cavities
surface smoothness <= -0.1 mm/cm2 within contour; no
cracks; no pollution (fat, oil dust, etc.)
Minimum moving force of WP
switch
40gf (Ensures that the WP switch will not slide while it is
inserted to the connector).
WP Switch cycles minimum 1000 Cycles (@ Slide force 0.4N to 5N)

Note (1): The SDA’s recommended test methods for Torque, bending and Warpage are defined in seperate Application
Notes document.

Table 63: Reliability and Durability

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8.1.4 Electrical Static Discharge (ESD) Requirements
ESD testing should be conducted according to IEC61000-4-2
Required ESD parameters are:

(1) Human body model +- 4 KV 100 pf / 1.5 Kohm
(2) Machine model +- 0.25 KV 200 pf / 0 ohm
Contact Pads:

+/- 4kV, Human body model according to IEC61000-4-2

Non Contact Pads area:

+/-8kV (coupling plane discharge)
Human body model according to IEC61000-4-2
The SDA’s recommended test methods for the non-contact/air discharge tests are given in a

separate Application Note document.

Quality assurance

The product traceability shall be ensured by an individual card identification number.

+/-15kV (air discharge)

8.1.5

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8.2 M echanical form factor
The following 3 technical drawings define the card package of SD Memory Card with 2.1+/-0.15mm
card thickness (the Thin SD Memory Card drawings are given in Chapter 8.4 ).

ElectronicsCo., Ltd.
Figure 59: SD Memory Card - Mechanical Description (1 out of 3)
Notes for all the mechanical descriptions of the SD Memory Card (including Thin SD Memory Card):
1) The numbers enclosed by a square means that it is the distance between base lines. Those values
are for information only (the given general tolerances are not related to them).
DO NOT COPY (c)2000 (c)2001 by SD Group (MEI,SanDisk,Toshiba)

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ElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card mechanical specification
Figure 60: SD Memory Card - Mechanical Description (2 out of 3)
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card mechanical specification
Figure 60: SD Memory Card - Mechanical Description (2 out of 3)
CONFIDENTIAL

SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01 SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card mechanical specification

TaisolElectronicsCo., Ltd.Inter Connect
Area
Substrate
Area
Note: Refer to Table 62 for the definition of ’substrate’ and ’Inter Connect’ areas.

Figure 61: SD Memory Card - Mechanical Description (3 out of 3)

Figure 62 describes the Write Protect switch position at all various cases and card types.

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TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card mechanical specification
Figure 62: W P Switch definition for all cases and card types
8.3 System : card and connector
The description of the connector is out of the scope of this document. However, minimal recommendations
to the connector comprise the ability to guarantee Write Protect and Card Detection, hot
insertion and removal of the card, and to prevent inverse insertion.
8.3.1 Card hot insertion
To guarantee a reliable initialization during hot insertion, some measures shall be taken on the host
side. For instance, a special hot-insertion capable card connector may be used to guarantee the
proper sequence of card pin connection.
The card contacts are contacted in three steps:
1) Ground Vss (pin 3) and supply voltage Vdd (pin 4).
2) CLK, CMD, DAT0, DAT1, DAT2 and Vss (pin 6).
3) CD / DAT3 (pin 1).
Pins 3 and 4 should make first contact when inserting, and release last when extracting.
As another method, a switch could ensure that the power is switched on only after all card pads are
contacted. Of course, any other similar mechanism is allowed.
8.3.2 Inverse insertion
Inverse insertion is prevented by the reclining corners of SD Memory Card and connector.
-R/W card(WP switch is movable)
-ROM card(WP area is fixed)
Write unableWrite enableThis form is same as
taking off the WP Switch
from R/W card.
This is the case of 1.4mm
card which does not support
the WP switch.
Pulling downthe WP Switch.
Pulling up theWP Switch.
-R/W card(WP switch is movable)
-ROM card(WP area is fixed)
Write unable Write enable
This form is same as
taking off the WP Switch
from R/W card.
This is the case of 1.4mm
card which does not support
the WP switch.
Pulling down
the WP Switch.
Pulling up the
WP Switch.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card mechanical specification
Figure 62: W P Switch definition for all cases and card types
8.3 System : card and connector
The description of the connector is out of the scope of this document. However, minimal recommendations
to the connector comprise the ability to guarantee Write Protect and Card Detection, hot
insertion and removal of the card, and to prevent inverse insertion.
8.3.1 Card hot insertion
To guarantee a reliable initialization during hot insertion, some measures shall be taken on the host
side. For instance, a special hot-insertion capable card connector may be used to guarantee the
proper sequence of card pin connection.
The card contacts are contacted in three steps:
1) Ground Vss (pin 3) and supply voltage Vdd (pin 4).
2) CLK, CMD, DAT0, DAT1, DAT2 and Vss (pin 6).
3) CD / DAT3 (pin 1).
Pins 3 and 4 should make first contact when inserting, and release last when extracting.
As another method, a switch could ensure that the power is switched on only after all card pads are
contacted. Of course, any other similar mechanism is allowed.
8.3.2 Inverse insertion
Inverse insertion is prevented by the reclining corners of SD Memory Card and connector.
-R/W card(WP switch is movable)
-ROM card(WP area is fixed)
Write unableWrite enableThis form is same as
taking off the WP Switch
from R/W card.
This is the case of 1.4mm
card which does not support
the WP switch.
Pulling downthe WP Switch.
Pulling up theWP Switch.
-R/W card(WP switch is movable)
-ROM card(WP area is fixed)
Write unable Write enable
This form is same as
taking off the WP Switch
from R/W card.
This is the case of 1.4mm
card which does not support
the WP switch.
Pulling down
the WP Switch.
Pulling up the
WP Switch.
CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card mechanical specification
Figure 63: Inverse insertion
8.3.3 Card Orientation
For the benefit of unified terminology when discussing the three dimensional orientation of a card
(e.g. for connector definition), the non contact-pads side (the side with the card label) is defined as
the TOP side of the card and the contact-pads side of the card is defined as the BOTTOM side of
the card.
8.4 Thin (1.4mm ) SD Memory Card
SD Memory cards with mechanical dimensions that will be suitable for extra small applications will
be available.
The "Thin SD Memory card" has very similar form factor as the SD Memory Card that is given in
Chapter 8.2 above except it thickness. The thickness of the "Thin SD Memory Card" is 1.4mm+/0.15mm.
Figure 64, 65 and 61 are the mechanical drawings of Thin SD Memory Card.
Note that even though the WP switch appears in the given diagram it was defined as an optional for
Thin SD Memory Card.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card mechanical specification
Figure 63: Inverse insertion
8.3.3 Card Orientation
For the benefit of unified terminology when discussing the three dimensional orientation of a card
(e.g. for connector definition), the non contact-pads side (the side with the card label) is defined as
the TOP side of the card and the contact-pads side of the card is defined as the BOTTOM side of
the card.
8.4 Thin (1.4mm ) SD Memory Card
SD Memory cards with mechanical dimensions that will be suitable for extra small applications will
be available.
The "Thin SD Memory card" has very similar form factor as the SD Memory Card that is given in
Chapter 8.2 above except it thickness. The thickness of the "Thin SD Memory Card" is 1.4mm+/0.15mm.
Figure 64, 65 and 61 are the mechanical drawings of Thin SD Memory Card.
Note that even though the WP switch appears in the given diagram it was defined as an optional for
Thin SD Memory Card.
DO NOT COPY (c)2000 (c)2001 by SD Group (MEI,SanDisk,Toshiba)

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TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card mechanical specification
Figure 64: Mechanical Drawing of Thin SD Memory Card
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card mechanical specification
Figure 64: Mechanical Drawing of Thin SD Memory Card
CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card mechanical specification
Figure 65: Mechanical Drawing of Thin SD Memory Card
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
SD Memory Card mechanical specification
Figure 65: Mechanical Drawing of Thin SD Memory Card
CONFIDENTIAL

TaisolElectronicsCo., Ltd.
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
Appendix
9 Appendix
9.1 Power Supply Decoupling
The VSS1, VSS2 and VDD lines supply the card with operating voltage. For this, decoupling capacitors
for buffering current peak are used. These capacitors are placed on the bus side corresponding
to Figure 66.
Figure 66: Power supply decoupling
The host controller includes a central buffer capacitor for VDD. Its value is 1 ?F/slot
9.2 Connector
The connector described in this chapter serves as an example and is subject to further changes.
9.2.1 General
The connector housing which accommodates the card is formed of plastic. Inside are 9 contact
springs for contacting the pads of the inserted card. As an option a Write Protect/Card Detection
C
Lmax = 13 mm
VSS1
VSS2
VDD
SD Memory Card
single card slot
single card slot
C=100 nF
SD-Memory Card Specifications / Part 1. Physical Layer Specification; Version 1.01
Appendix
9 Appendix
9.1 Power Supply Decoupling
The VSS1, VSS2 and VDD lines supply the card with operating voltage. For this, decoupling capacitors
for buffering current peak are used. These capacitors are placed on the bus side corresponding
to Figure 66.
Figure 66: Power supply decoupling
The host controller includes a central buffer capacitor for VDD. Its value is 1 ?F/slot
9.2 Connector
The connector described in this chapter serves as an example and is subject to further changes.
9.2.1 General
The connector housing which accommodates the card is formed of plastic. Inside are 9 contact
springs for contacting the pads of the inserted card. As an option a Write Protect/Card Detection
C
Lmax = 13 mm
VSS1
VSS2
VDD
SD Memory Card
single card slot
single card slot
C=100 nF
DO NOT COPY (c)2000 (c)2001 by SD Group (MEI,SanDisk,Toshiba)

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Appendix

switch shall be part of the housing in order to be able to detect the position of the Write Protect sliding
tablet on the card. Testing procedures are performed according to DIN IEC 68.

9.2.2 Card Insertion and Rem oval
Insertion of the SD Memory Card is only possible with the contact area of the card and the contact
area of the connector in the correct position to each other. This is ensured by the reclining corners
of the card and the connector, respectively.

To guarantee a reliable initialization during hot insertion, some measures must be taken on the host
side. One possible solution is shown in Figure 67. It is based on the idea of a defined sequence for
card contact connection during the card insertion process. The card contacts are contacted in three
steps:

Ground Vss (pin 3) and supply voltage Vdd (pin 4).

CLK, CMD, DAT0, DAT1, DAT2 and Vss (pin 6).

The pins 3 and 4 should make first contact when inserting and release last when extracting.

3) CD / DAT3 (pin 1).

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Appendix

Figure 67: Modified SD Memory Card connector for hot insertion

9.2.3 Characteristics
The features described in the following must be considered when designing a SD Memory Card
connector. The given values are typical examples.

‧ Mechanical Characteristics
-Max. number of mating operations > 10000
-Contact force 0.2 N (minimum contact force per one contact)
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Appendix

-Total pulling force min.1 N DIN IEC 512 part 7
-Total insertion force max. 40 N DIN IEC 512 part 7
-Vibration and High Frequency
-Mechanical frequency range 10.....2000 Hz DIN IEC 512 part 2 and 4
-Acceleration 2 g
-Shock:
-Acceleration 5 g
‧ Electrical Characteristics
DIN IEC 512

-Contact resistance 100 m?
-

Current carrying capacity at 25°C 0.5 AInsulation resistance > 1000 M? ??> 100 M? after test

3.3 V
500 V
Clim atic Characteristics

Operating temperature
Storage temperature

Operating voltage

Testing voltage

Operating current

100 mA max.

-25°C.....90°C-40°C.....90°C95% max. non condensing

‧

DIN IEC 512 part 6-9

Humidity

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Appendix

- This page was left empty intentionally

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10 Abbreviations and terms

block a number of bytes, basic data transfer unit
broadcast a command sent to all cards on the SD bus
CID Card IDentification number register
CLK clock signal
CMD command line or SD bus command (if extended CMDXX)
CRC Cyclic Redundancy Check
CSD Card Specific Data register
DAT data line

DSR

ECC

Flash

group
LOW, HIGH

NSAC

MSB, LSB

MTP

OCR

open-drain

OTP

payload

push-pull

RCA

ROM

sector
stuff bit

a number of sectors, composite erase and write protect unit
binary interface states with defined assignment to a voltage level

defines the worst case for the clock rate dependent factor of the data access time
the Most Significant Bit or Least Significant Bit
Multiple Time Programmable memory
Operation Conditions Register
a logical interface operation mode. An external resistor or current source is used

to pull the interface level to HIGH, the internal transistor pushes it to LOW
One Time Programmable memory
net data
a logical interface operation mode, a complementary pair of transistors is used

to push the interface level to HIGH or LOW
Relative Card Address register
Read Only Memory
a number of blocks, basic erase unit

Driver Stage Register
Error Correction Code
a type of multiple time programmable non volatile memory

filling bits to ensure fixed length frames for commands and responses

Serial Peripheral Interface

defines the time dependent factor of the data access time

marker used to select groups or sector to erase

To Be Determined (in the future)

a driver stage which has three output driver states: HIGH, LOW and high imped

ance (which means that the interface does not have any influence on the inter

face level)

code word representing a command

SPI

TAAC

tag
TBD

three-state driver

token

VDD + power supply
VSS power supply ground

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